verilog A difference between <= and <+

[Aforak]

hi dudes,

plz answer this
whats the difference between <= and <+ in verilog A

thank you

 

[dave_59]

There is no <+ operator in Verilog

 

[Aforak]

dude! Iam asking about verilog-A, used for analog models

 

[imbichie]

Hi Aforak,

From my understanding we must use the <+ when we are dealing with analog signals like V(out), I(in1, in2) etc. For driving these signals we need to use <+.

But if the signal is not an analog then we can use the <=.

 

[Aforak]

Yup got it
shibin

Thank you
aforak