Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
always @(negedge clk or posedge reset) begin
if (reset==1) begin
out1<=1'b0;
count<=8'h00;
end
else if (dbn_en==1 && enable==1) begin
if (n[0]==0) begin // even count
if (count==m-1)begin
count<=8'h00;
out1<=~out1;
end
else
count<=count+1;
end
else if (count==n-1)begin // odd count
count<=8'h00;
out1<=~out1;
end
else
count<=count+1;
end
end
assign m=n>>1;
always @(posedge clk or posedge reset) begin
if (reset==1) begin
out2<=1'b0;
end
else if (count==m && enable==1)
out2<=out1;
end
Hello dear..
Its nice that u post the code here.
I want to ask is this code be used in Charge Pump PLL for the Feedback Divider Block?
Its like a Programmable Feedback divider..Am i right?
Added after 1 minutes:
assign out=(enable==1)?((dbn_en==0)? clk n[0]==1)? out1^out2 : out1):1'b0;
whats that Face showing in this line?
hi friend , here in this problem input is given clock and duty cycle , if i want 40% duty cycle it should give 40% duty cycle etc.. Now can I give (duty cycle) * Tclk*n as high level output and Tclk*n*(1.duty cycle) as low level output , can u give me code for this .. ?/?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.