verilog a code for divide by n

verilog divide

hi,can i anyone give me verilog A code for divide by n counter for input clock and given duty cycle ..

divide in verilog

module Divide_N ( reset, clk, enable, n, clk_out );

input clk;
input reset;
input enable;
input [7:0] n;
output clk_out;

wire [7:0] m;
wire dbn_en;
reg [7:0] count;
reg out1;
reg out2;
wire out;
wire clk_out;

assign dbn_en = n[7] | n[6] | n[5] | n[4] | n[3] | n[2] | n[1];

always @(negedge clk or posedge reset) begin
if (reset==1) begin
out1<=1'b0;
count<=8'h00;
end
else if (dbn_en==1 && enable==1) begin
if (n[0]==0) begin // even count
if (count==m-1)begin
count<=8'h00;
out1<=~out1;
end
else
count<=count+1;
end
else if (count==n-1)begin // odd count
count<=8'h00;
out1<=~out1;
end
else
count<=count+1;
end
end

assign m=n>>1;

always @(posedge clk or posedge reset) begin
if (reset==1) begin
out2<=1'b0;
end
else if (count==m && enable==1)
out2<=out1;
end

assign out=(enable==1)?((dbn_en==0)? clk n[0]==1)? out1^out2 : out1):1'b0;

assign clk_out = out;

endmodule

verilog divide by 10

Hello dear..
Its nice that u post the code here.
I want to ask is this code be used in Charge Pump PLL for the Feedback Divider Block?
Its like a Programmable Feedback divider..Am i right?

Added after 1 minutes:

assign out=(enable==1)?((dbn_en==0)? clk n[0]==1)? out1^out2 : out1):1'b0;
whats that Face showing in this line?

verilog code divide

hi friend , here in this problem input is given clock and duty cycle , if i want 40% duty cycle it should give 40% duty cycle etc.. Now can I give (duty cycle) * Tclk*n as high level output and Tclk*n*(1.duty cycle) as low level output , can u give me code for this .. ?/?