verilog 3 bit up counter

[vead]

I need some help I want to write verilog code for up counter using D flip flop

table

N | A B C(current state) clk |next state
0 | 0 0 0 | ↑ 001
1 | 0 0 1 | ↑ 010
2 | 0 1 0 | ↑ 011
3 | 0 1 1 | ↑ 100
4 | 1 0 0 | ↑ 101
5 | 1 0 1 | ↑ 110
6 | 1 1 0 | ↑ 111
7 | 1 1 1 | ↑ 000

verilog code

module up_counter(current state, next state ,clk)
          input current state ;
          input clk;
          output next state;
          reg 3:0
          always @ (posedge clk);
          begin 
          next state <= current state +1 ;
          end
         endmodule

please help me to write code

 

[RiazHaider]

from what i can gather u need to design a state machine. You should read up on Mealy or Moore state machines. The code that you've written can work in principle. Just use a MAX value at 8 which can bring your counter back to '0'.

 

[yadavvlsi]

Please check below links:
**broken link removed**
https://www.asic-world.com/examples/verilog/up_down_counter.html

 

[ads-ee]

I need some help I want to write verilog code for up counter using D flip flop

table

N | A B C(current state) clk |next state
0 | 0 0 0 | ↑ 001
1 | 0 0 1 | ↑ 010
2 | 0 1 0 | ↑ 011
3 | 0 1 1 | ↑ 100
4 | 1 0 0 | ↑ 101
5 | 1 0 1 | ↑ 110
6 | 1 1 0 | ↑ 111
7 | 1 1 1 | ↑ 000

verilog code

module up_counter(current state, next state ,clk)
          input current state ;
          input clk;
          output next state;
          reg 3:0
          always @ (posedge clk);
          begin 
          next state <= current state +1 ;
          end
         endmodule

please help me to write code

This code doesn't have the correct declarations for the 3-bit state input/output ports, besides using the antiquated, university standard port declarations. You also can't have names with spaces in them "current state" is an invalid Verilog signal name. "reg 3:0" is syntactically incorrect. Have you read a Verilog book, have you looked online for any Verilog tutorials and/or coding examples? Have you downloaded the currently free IEEE 1800-2012 LRM specification?
This is how the ports should have been declared...

---

Code Verilog - [expand]
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module up_counter (
  input [2:0] current_state,
  input  clk,
  output reg [2:0] next_state
);

---

I'm actually not sure of your intent for the code with both the next_state and current_state being ports on your module. If you were supposed to implement the counter as an FSM (finite state-machine) then you shouldn't have the current_state or next state being ports of the module. Based on the name of the module a counter output should be the only port besides clock on the module. And based on the next_state/current_state nonsense, the instructor wants you to produce a two always block FSM.

---

Code Verilog - [expand]
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module up_counter (
  input clk,
  output [2:0] counter
);
 
  reg [2:0] current_state = 3'b0;
  reg [2:0] next_state;
 
  // current_state flip-flop
  always @ (posedge clk) begin
    current_state <= next_state;
  end
 
  // FSM transitions
  always @* begin
    case (current_state)
      0 : next_state <= 1;
      1 : next_state <= 2;
      // etc...
      7 : next_state <= 0;
      default : next_state <= 3'bxxx; // just to let you know currrent_state went x/u/z
    endcase
  end
 
  assign counter = current_state;
endmodule

---

The code that you've written can work in principle. Just use a MAX value at 8 which can bring your counter back to '0'.

The code won't work based on what I've already pointed out. And if you use a MAX value of 8 then you would actually have to reach 8 to cycle back to 0, which isn't a 3-bit counter and will cycle with a count of 0-8 not 0-7. MAX value should be 7, but that isn't necessary as 3-bits will rollover from 7 to 0 on it's own with no extra check for a max value.