[SOLVED] Verilog 2001 indexed part-select +: in always block

[ShanghaiDSP]

Hi to all,

I'm writing a generic multiplexer and facing a problem regarding Verilog.

I try to use a for-loop (with bounded index - to keep it synthesizable) and
assign a sliced part of the input to the output depending on cnt (one-hot encoded).
The idea is to slice a wide input vector (e.g. 128 bit) to a narrow (e.g. 32 bit) output
but in a generic way, so bit widths may change.
Consider the following code:

integer i;
always@(*) begin
	data_o =  data_mux[LINK_WIDTH-1 : 0]; 
	for(i=0; i < SERDES_LEVEL ; i= i+1) 
		begin
			if(cnt[i] == 1'b1) 
				begin
					data_o =  data_mux[((i+1)*LINK_WIDTH-1) +: (LINK_WIDTH*i)];
				end	
		end
		
	end

According Verilog 2001 spec the "+: " operator should be used,
because ":" is not sufficient when a index variable is involved.
But ModelSim 10.4 reports "Range width must be constant expression." for the "data_o = data_mux[((i+1)*LINK_WIDTH-1) +: (LINK_WIDTH*i)];" assignment
(verilog files are compiled as verilog 2001 version).
I checked several times...the width of sliced vector part is not changing during loop iterations.

For me this behavior is not understandable, starting from the introduction of indexed part-select "+:" operator. I can agree if someone tries to use a unbound for loop or the indexed bit width is changing. But verilog compiler just refuse in any case even if its a (in general) valid code.

Would be nice if someone could explain these limitation to me or where the error is :grin:

 

[iamyuchenjie]

I will try lovely ncsim for u

Hi to all,

I'm writing a generic multiplexer and facing a problem regarding Verilog.

I try to use a for-loop (with bounded index - to keep it synthesizable) and
assign a sliced part of the input to the output depending on cnt (one-hot encoded).
The idea is to slice a wide input vector (e.g. 128 bit) to a narrow (e.g. 32 bit) output
but in a generic way, so bit widths may change.
Consider the following code:

integer i;
always@(*) begin
	data_o =  data_mux[LINK_WIDTH-1 : 0]; 
	for(i=0; i < SERDES_LEVEL ; i= i+1) 
		begin
			if(cnt[i] == 1'b1) 
				begin
					data_o =  data_mux[((i+1)*LINK_WIDTH-1) +: (LINK_WIDTH*i)];
				end	
		end
		
	end

According Verilog 2001 spec the "+: " operator should be used,
because ":" is not sufficient when a index variable is involved.
But ModelSim 10.4 reports "Range width must be constant expression." for the "data_o = data_mux[((i+1)*LINK_WIDTH-1) +: (LINK_WIDTH*i)];" assignment
(verilog files are compiled as verilog 2001 version).
I checked several times...the width of sliced vector part is not changing during loop iterations.

For me this behavior is not understandable, starting from the introduction of indexed part-select "+:" operator. I can agree if someone tries to use a unbound for loop or the indexed bit width is changing. But verilog compiler just refuse in any case even if its a (in general) valid code.

Would be nice if someone could explain these limitation to me or where the error is :grin:

 

[ads-ee]

It's defined like this:
[Least_significant_bit_of_slice +: the_width_of_the_slice]

The width of the slice is not variable, only the starting bit.

 

[iamyuchenjie]

It's defined like this:
[Least_significant_bit_of_slice +: the_width_of_the_slice]

The width of the slice is not variable, only the starting bit.

Thank you very much！It wokrs

 

[ShanghaiDSP]

Thanks, you are right!
if you are used to [MSB:LSB] notation this +: operator is not straightforward :-?

It's defined like this:
[Least_significant_bit_of_slice +: the_width_of_the_slice]

The width of the slice is not variable, only the starting bit.

 

[ads-ee]

Thanks, you are right!
if you are used to [MSB:LSB] notation this +: operator is not straightforward :-?

Not sure why it's always considered confusing by so many as it's described pretty good in the LRM:




As you can see it says right there K must be a constant.