Verification tips and advices needed

[fcfusion]

Hi everyone

I need some tips from experienced engineers regarding HDL verification.

I've been working for a few months on FPGA Development and my main task is to perform verification. Basically, some one gives a bunch of VHDL code, tells me what it is supposed to do, and I have to test it with some ideal models created by me to see if it works. The entire verification is performed in VHDL, including the models, and I find it quite hard to develop models to match the real circuit especially for very complex projects.

One of my main difficulties is that the VHDL seems like a poor language for verification: processes require very large sensitivity lists, signal's values are only updated on the next clock cycle (as if they were registers) adding unwanted signal delays, etc ...

I have some background in C, and sometimes I feel as if C was a much better language to simulate these models and compare results. I've heard some people use Pearl.

What do you guys have to say about this? How do you guys perform functional verification? Which tools do you use? Where can I get more information about good verification methods?

 

[blooz]

These are some good links to start with

1.h**p://www.ovmworld.org/

2.h**p://www.open-vera.com/

3.h**p://verificationguild.com/

4.h**p://www.uvmworld.com/

....You can use Verilog Also ..

 

[TrickyDicky]

you can do alot with VHDL. You have to remember that in testbenches you can do pretty much anything. There is no need to write RTL synthesisable logic, so you can go crazy. Make use of file IO, access types, behavioural models divorced from the clocks and all that stuff. its very difficult to explain all of this in one large book-sized post as there is plenty of literature on the subject. I can highly recommend "Writing Testbenchs - Functional Verification of HDL Models" by Janick Bergeron. It covers plenty of verification theory with some code examples.

To explain anything further you really need to post some more specific questions, as it is a MASSIVE subject.

quick tips:
Forget about sensitivity lists. Use wait statements in testbench processes:

some examples:
wait until rising_edge(clk) and data_valid = '1'
wait on restart_test'transaction;

learn about File IO. With modelsim you can directly read/write binary files via a bit of a work around, but it means you can read/write directly to bitmaps (great for data visualisation or if you're doing image processing)

Access types make some things really neat. You can easily write a sparce memory model that allows you to model a very large ram without using 100s of MB of system memory.

And finally, build up a library of functions/procedures/protected types that you use alot.

 

[fcfusion]

That's for the reply, I'll take a look at those sites as soon as possible.

I use Verilog in my home projects, but in the company I work for there are strict rules regarding the Verilog. Only VHDL is allowed.

 

[TrickyDicky]

Also with access types - these allow you to build linked lists - helpful in some situations when testing or writing behavioural models (you could build a behavioral fifo model using a linked list).

 

[fcfusion]

To explain anything further you really need to post some more specific questions, as it is a MASSIVE subject.

Indeed.

Forget about sensitivity lists. Use wait statements in testbench processes.

Funny, I learned that by my self the hard way.

And finally, build up a library of functions/procedures/protected types that you use alot.

Funny again, I learned that by myself the hard way as well.

Access types make some things really neat. You can easily write a sparce memory model that allows you to model a very large ram without using 100s of MB of system memory.

Didn't know that. This could be very usefull.

Thank you for your reply, it was very helpfull. I'm gonna take a look at these things.

 

[TrickyDicky]

here is a DDR model that I wrote. It basically sets up an array of 8 pointers, which in turn are arrays of pointers. These are unallocated until specific addresses are written. I also have wipe functions to deallocate the whole thing, or specific parts, but I havent included them here:

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
type ddr_model_t is protected
  impure function read( addr : unsigned(25 downto 0) ) return std_logic_vector;
  procedure write(      addr : unsigned(25 downto 0); 
                        data : std_logic_vector(31 downto 0)
                 );
  
end protected ddr_model_t;
 
-----------------------------
--BODY of ddr_model_t
----------------------------- 
type ddr_model_t is protected body
  
  type bank_t;
  type row_t;
  
  type row_ptr_t is access row_t;
  type bank_ptr_t is access bank_t;
  
  type row_t  is array(0 to 1023) of std_logic_vector(31 downto 0);
  type bank_t is array(0 to 8191) of row_ptr_t;
  
  ---------------------------------------------------------------------
  --Total mem is 8 banks x 8192 rows x 1024 columns x 32 bits/word
  --
  -- = 256 Mbyte
  ---------------------------------------------------------------------
  type mem_t is array(0 to 7) of bank_ptr_t;
  
  variable mem              : mem_t;
  
  impure function read(addr : unsigned(25 downto 0) )  return std_logic_vector is
    variable bank           : integer;
    variable row            : integer;
    variable column         : integer;
    
    variable ret            : std_logic_vector(31 downto 0);
  begin
    
    bank     := to_integer( addr(25 downto 23) );
    row      := to_integer( addr(22 downto 10) );
    column   := to_integer( addr( 9 downto  0) );
    
    ---------------------------------------------------------
    --Bank has not been written to, therefore not created
    ---------------------------------------------------------
    if mem(bank) = null then
      ret := (others => 'X');
      
    ---------------------------------------------------------
    --Row has not been written to, therefore not created
    ---------------------------------------------------------
    elsif mem(bank)(row) = null then
      ret := (others => 'X');
      
    ------------------------------------------
    --Return what has been written already
    ------------------------------------------
    else 
      ret :=  mem(bank)(row)(column);
    end if;
      
    return ret;   
  end function read;
 
 
  procedure write(      addr : unsigned(25 downto 0); 
                        data : std_logic_vector(31 downto 0)
                 ) is
    variable bank           : integer;
    variable row            : integer;
    variable column         : integer;
  begin
    
    bank     := to_integer( addr(25 downto 23) );
    row      := to_integer( addr(22 downto 10) );
    column   := to_integer( addr( 9 downto  0) );
    
    --------------------------------------------------
    --Create the bank if it doesnt already exist
    --------------------------------------------------
    if mem(bank)   = null then
      mem(bank)   := new bank_t;
    end if;
    
    ---------------------------------------------
    --Create the row if it doesnt already exist
    ---------------------------------------------
    if mem(bank)(row) = null then
      mem(bank)(row)     := new row_t;
    
      mem(bank)(row).all := (row_t'range => (others => 'X'));
    end if;
    
    mem(bank)(row)(column) := data;
  end procedure write;
end protected body ddr_model_t;

---

---------- Post added at 10:21 ---------- Previous post was at 10:19 ----------

ps - I love protected types.

---------- Post added at 10:33 ---------- Previous post was at 10:21 ----------

Another thing to add - VHDL has a random number generator in the math_real library called uniform. It generates reals in the range 0-1, which you can use to create random anything.