Verification Questions in Interviews

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bismillah

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Hi,

I will be facing interview for verification engineer job with a client. Can anybody please tell me what questions to expect and what are the answers.

Thanks in advance
 

u can be asked about formal verification, verification enviornment, checkerboard methodology, bfm..
 

bismillah said:
Hi,

I will be facing interview for verification engineer job with a client. Can anybody please tell me what questions to expect and what are the answers.

Thanks in advance
Click to expand...

Lot of Interview question can be found Here:

https://vlsifaq.blogspot.com/
 

thanks, its a great help for me.
 

Thanks,
Is there a way one can obtain some hands on training in verification with HVL like Vera, systems verilog, system c, with self learning tutorials?
 

Read the things about Code Coverage , there is paper from Mentor Ghraphics AVM " Adavance Verification methodologies " that is really useful people for newbie's and learners .

shobhitkapoor[at]gmail[dot]com

Added after 1 minutes:

Yes posible with System Verilog and SystemC find a demo modelsim from mentor ghraphics and download it on ure system ...find a tutorial of System Verilog ( Say www.asic-world.com ) and Start the desired Task
 

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