verification of layout cells with no schematic

[Old Nick]

I've been trying to work out a way of verifying that all contacts etc. are present on an array of CCD cells (it's a CCD array on CMOS technology) to which there is no schematic cell (I really just want to perform an LVS on the array). The problem is there is no real circuit in the pixels it is just 4 metal paths going from one end to the other end (the 4 clock phases P1 to P4) of the cell with taps to the substrate where there is amongst other things 2 customer specific layers (we're not the customer so don't know what they are exactly), so I can't create a schematic cell for it. Anyway when the pixels are arranged in an array all of the p1's are connected together (as are the other phases), one missing via, an extra via where there shouldn't be one or a misplaced slot etc. leaving only 1 row unconnected could spell disaster for the device. I can scan all over the array by eye and highlight nets and all that to try and convince myself that everything is as it should be, but this strikes me as a terrible (and unsafe) way to perform verification. I've had several ideas, such as adding structures (small capacitances) to the end of the phases at each row so I can build some sort of schematic to compare it to, but there are several errors I can think of that this wouldn't catch.
What would be ideal is if I could do a resistive extraction to get a resistance for the metal tracks across each pixel then create a schematic with these resistances added, but I think LVS isn't going to know the extracted circuit to compare against such a schematic, or at least I don't think it would be able to (our license server is down at the moment so I can't check this).
There must be a clever way of doing this surely, I just can't think of it. Any advice would be greatly appreciated.

Cheers.

 

[dick_freebird]

You might think about making a start-from-zero layout
that consists of the features you want to check, made
by other means (say, an array or plurality-of-arrays, or
array-of-plural contacts stepped at the know construction.
Then XOR this against the same layer of the real layout
and key on any discrepancies.

Not as good as a true LVS, but at least an honest cross
check based on expectations of content.

Then again, how difficult can it be to create the schematic
for such a regular structure as the imager array? Some
work to find a CCD cell symbol w/ valid LVS rep, I suppose.

 

[Old Nick]

yeah, I don't think a schematic can be done as there's no components in it that LVS would know about. I tried making one with pins, one for each of the metal clock lines in the layout, but that just gives loads of warnings. It may be the only way to go though, but it seems wrong.