verification environment in vhdl

[kranthi_vlsi]

can we write environment kind of verification in vhdl(which is like in sys Verilog) . like all the tasks and its definition and declarations in one file and calling of these tasks in main testbench file

 

[axcdd]

I dont know if i got this right, but you can write functions and procedures in a package and include that package in testbench file.

 

[TrickyDicky]

What things are you trying to do? In VHDL, you can put procedures, functions, signals and plenty of other stuff in a package. You can even declare protected types (with vhdl 200X) that are similar to objects (ie. they have member functions, procedures, variables etc).

So what are you trying to do? AFAIK, there isnt really much you cant do with VHDL that you can do in SV.