Vending Machine using Verilog, Quartus 2, Altera DE2

[queencythea]

I HAVE THIS VERILOG CODE TO IMPLEMENT VENDING MACHINE ON MY ALTERA DE2 BOARD. IT WORKS BUT IT TRANSFERS TO THE NEXT STATE EVEN IF I INPUTTED NOTHING. PLEASE HELP.




module mealyvend(N, D, clk, reset, open);
// Mealy FSM for a vending machine
input N, D, clk, reset;
output open;
reg [1:0] pstate, nstate;
reg [0:6]open;
wire clk1Hz;
parameter S0=2'b00, S5=2'b01, S10=2'b10, S15=2'b11;
onesecond u1(clk,clk1Hz);
// Next state and ouptut combinational logic
always @(N or D or pstate or reset)
if (reset)
begin nstate = S0; open = 7'b0000001; end
else
case (pstate)
S0: begin open = 7'b0000001; if (N) nstate = S5;
else if (D) nstate = S10;
else nstate = S0; end

S5: begin open = 7'b0000001; if (N) nstate = S10;
else if (D) nstate = S15;
else nstate = S5; end

S10: if (N | D) begin nstate = S15; open = 7'b0000001; end
else begin nstate = S10; open = 7'b0000001; end

S15: begin nstate = S0; open = 7'b1001111; end
default: nstate=S0;
endcase
// FF logic, use nonblocking assignments "<="
always @(posedge clk1Hz)
pstate <= nstate;
endmodule

 

[beeflobill]

" IT WORKS BUT IT TRANSFERS TO THE NEXT STATE ...."

When does it work and when does it not work? Does it work in simulation and not on the fpga? Or, does the state machine simulation behavior mostly do like you want, but the value of nstate, pstate, or open isn't what you expect after you assert reset?

"IT TRANSFERS TO THE NEXT STATE EVEN IF I INPUTTED NOTHING"

What state is it going to and what state do you expect it to go to?

 

[queencythea]

" IT WORKS BUT IT TRANSFERS TO THE NEXT STATE ...."

When does it work and when does it not work? Does it work in simulation and not on the fpga? Or, does the state machine simulation behavior mostly do like you want, but the value of nstate, pstate, or open isn't what you expect after you assert reset?

"IT TRANSFERS TO THE NEXT STATE EVEN IF I INPUTTED NOTHING"

What state is it going to and what state do you expect it to go to?

I haven't tried to simulate it because i don't know how to generate its test bench. what i mean is that it has no errors but when i download the codes to the fpga, it just transfers from one state to another, like a counter. i would like to use the fpga push buttons for the 2 coins. is it my clock? i'm using 1hz. please help this is my thesis. regards

 

[mrflibble]

I haven't tried to simulate it because i don't know how to generate its test bench.

**broken link removed**
http://www.doulos.com/knowhow/verilog_designers_guide/test_benches/
http://www.asic-world.com/verilog/art_testbench_writing.html‎

should get you started

 

[beeflobill]

I don't know how to setup your inputs as buttons with your development board. I don't know how to setup your outputs either.

However, if I were you I'd do a few things.

1) I'd make D, N, and reset buttons on your development board. Maybe you have already done this.

2) Keep using the internal clock just like you are using (1Hz is a good speed to debug).

3) I don't completly understand your problem, but maybe the issue is that if your keeping the input coin buttons, like D, held down, that the state machine is looping around. Perhaps a way to solve that would be to add in an additional state which will wait for the coin input to be zero before the state machine goes into a waiting state (I guess S0).

4) Change how the reset is implemented so it looks kindof like below. I don't know if this is the source of your problems or not, it's my opinion that this setup will cause you less problems.

always @(N or D or pstate) begin
   case (pstate)
   ...
   endcase
end

// FF logic, use nonblocking assignments "<="
always @(posedge clk1Hz or posedge reset) begin
   if (reset)
      pstate <= S0;
   else
      pstate <= nstate;
end
endmodule

I put together a quick little testbench for the module you gave. I don't know how you could or would use it. But, I'd suggest that you would try to work out every issue you can think of in simulation before you try the fpga. You could create a task like insert_coin_d which would give input stimulus to the module that would be like someone inserting a D coin. That way you can see what the state machine should be doing.

module bench();

   reg N, D, clk, reset;
   wire [6:0] open;

   mealyvend DUT (N, D, clk, reset, open);

   task do_clk;
      input integer times;
      integer i;
      begin
         for (i=0; i<times; i=i+1) begin
            clk = 1'b1;
            #10;
            clk = 1'b0;
            #10;
         end
      end
   endtask

   initial begin
      N = 1'b0;
      D = 1'b0;
      clk = 1'b0;
      reset = 1'b0;
      #10;

      reset = 1'b1;
      #10;
      do_clk(10);

      reset = 1'b0;
      #10;
      do_clk(10);

      D = 1'b1;
      #10;
      do_clk(10);

      D = 1'b0;
      #10;
      do_clk(10);

      N = 1'b1;
      #10;
      do_clk(10);

      N = 1'b0;
      #10;
      do_clk(10);

      D = 1'b1;
      N = 1'b1;
      #10;
      do_clk(10);

      #500;
   end
endmodule

 

[ads-ee]

As beeflobill says the reset implementation should be on the register not the combinatorial logic. You should add a state after S15 to cycle until both N & D are inactive..

---

Code Verilog - [expand]
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S15_PLUS : begin
  if ( !N && !D ) begin
    nstate = S0;
    open = 7'b0000001;
  end else
    nstate = S15_PLUS;
    open = 7'b0000001;
  end
end

---

which will keep the FSM from cycling if the N & D stay active for longer than the FSM takes to transition through all the states.

Regards