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Vds-Vdsat to keep a transistor in saturation

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PSG

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Hi,

This probably sounds like a dumb question, but if I want to keep my MOS in saturation, I know I need to keep the Vds large enough, and instinctively it would make sense to keep it above Vdsat ... if I missed something already, stop me right there!
So now the question is how much margin do I allow myself: is Vds-Vdsat>0 enough or do I need to have Vds-Vdsat>100mV to play safe. At the other end, in situations where I run out of headroom, can I go with Vds slightly below Vdsat, and if so what is the trade-off.

Thanks in advance for your advice.
 

PSG

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bump
 

snafflekid

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Vds>Vgs-Vt is the definition of saturation. In short channel mosfets this is not exact but good enough. If your working circuit depends on 100mV difference on the drain, you must run many test case simulations.
 

ravirajdv

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Hi,
Vds-Vdsat=0 is on the verge of saturation (pinch off point). It is better to keep a margin of 100mV - 200mV so that you take care of the effects that exist because of process. supply and temperature variations.
Higher the margin lesser are the effects of the noise, specifically the thermal.

Regards,
RDV
 

DenisMark

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Hi PSG,

Vds-Vdsat>0 is ok (if you keep it for all process corners as well as for bias conditions and temperatures).
Indeed in model Vdsat is actually overestimated. It's higher than point below which Rds starts to reduce.
You can find it out e.g. in:
Tradeoffs and Optimization in Analog CMOS Design by David Binkley
 

oht993

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In hspice sim result, make Vod lager than Vdsat..
 

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