VDD/VSS ESD protection issue

[trashbox]

esd protection how it works

Hi all,
As the attachment, the left-side is a general vdd/vss ESD protection circuit. How the M1/M2 works when it is under Positive-mode ESD test as described in the right-side? Thanks in advance!

--Trashbox

 

[mengcy]

vdd vss esd

read the basic ESD theory of reference books.
for example,the art of analog layout,

 

[erikl]

M1 and/or M2 limit the ESD voltage due to their S-D breakdown mechanism.

 

[srftech]

Building on to Erikl's response, remember the NMOS has a parasitic NPN and the PMOS a parasitic PNP, now without process information I will just say this..generally the NPN will do the brunt of the ESD protection in this case...so what will happen is as Erikl mentioned, the Drain-bulk junction of the NMOS will avalanche and initiate what is referred to as snapback where the NPN will parasitically turn on and help clamp the ESD event to Vss, as you have it depicted. This is a very crude explanation, and as was recommended, you should check out some of the references for further detail.

Excellence in ESD and IO Design