VDD/VDDA GND Seperation - analod/sc/digital/padring

[Sonnenmann]

we design a mixed signal chip with three main parts:
- sensible analog
- switched capacitor based adc
- logic part

all these parts are connected to a the padring, which build up by standard digital output cells, and ESD protected analog cells.
Now my question is - how should we seperate the power lines. I know we have to seperate vdd(digital) and vdda(analog) but what should i do with VDDA of SC Circuits and with the power of padring(digital outbut buffer and esd diode connection)

i want to minimize crosstalk and clockfeedthrough to all analog - and to ensure i high snr for adc.

Second question: Should i separate digital ground and analog ground, too? How can i do this because LVS notice the connection about substrat and give me an error,

 

[erikl]

If you can afford enough power & gnd pads and pins, I think it would be wise to use different (layout) nets for all GND and VDD supplies (i.e. gnd(digital), gnda(analog), gndsc(analog), vdd(digital), vdda(analog), vddsc(analog)), use extra ESD protections for each supply pair, and connect the (common) GND and VDD supply externally (on the PCB) to the corresponding pins (together with individual decoupling caps).

You can at least use different vdd nets with their own routing, ESD protection, and pads. If your design system won't allow for separate gnd nets, you can still use separate routing to separate pads.

Some design systems provide an option to use different gnd net names by adding a "soft connection" property to the substrate connection.

 

[sdedov]

I agree with the comment above but have couple comments:
- if you use standard IO cells from fab/IP supplier, such set often contains the separate digital/analog IO cells.
- if you use manufacturer's PDK it usually provides an ability to separate the different gnds. Generally it's a
special layer to cover all gnd islands (may be except one of them).