VCS using compiled vhdl lib with verilog

[meir]

Hi All
I have created a compiled library using

vhdlan -w xilinxcorelib -f xilinxcorelib/xilinxcorelib_compile_order.do

When this library is compiled with a verilog file list
(i.e. the verilog file list includes +vhdllib+<lib>)

vcs -f <verilog_file_list>

I get :
Error-[VLIB_LIBUNMAPPED] Missing library map
Previously analyzed design unit resides in library 'IEEE', which has since
become unmapped.
The show_setup command shows all of the mappings for the libraries. Please
use this command to validate that the named library above is mapped to a
physical directory in your synopsys_sim.setup file.

Any ideas ?