VCO design and sizing

[jihrenee]

The image shown is a delay cell, where Vctrl is the control voltage. Where

MC: a current source work in triode region
MX: a negative resistance
MK: adjustable resistor
M+, M-: input pair

Connecting the delay cells in a loop will form a VCO.
Next, given Kvco, how can i size the MOS in this VCO to satisfy Kvco?
What i know so far is, i keep adjusting the size of MOS, run the simulation and draw the curve to calculate Kvco.
But strategy above is known as "hspice monkey" --- i'm just keep adjusting the size of MOS to ensure that the VCO will oscillate, and has enough swing.
Any direction to design a VCO?

 

[micpro]

What's wrong with "hspice monkey"? As soon as you have many second order effects and parasitics and transient specs, pure equation-based methods usually fail and simulation will play a key role in any sizing strategy.