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vco control voltage in pll behavioral simulation in simulink

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analog_ambi

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Hi,
i simulated my pll using simulink n time domain and ended up with peculiar control voltage even with 60 deg/75deg PM.

Fig 1 shows the output of loop filter. Fig. 2 shows output after VDD saturation. I want my vco control voltage to slightly rise from 0 at t=0 and settle as if critically damped.

Is it due very small ref frequency and high N=2500
fref=400khz fout=1Ghz N=2500

 

It depends upon your loop filter's dynamics. Loop bandwidth phase margin etc.Check with that.
 

I checked Phase margin and I get similar response even with 75 degree PM
 

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