Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VCO bias, regulator, phase noise

Status
Not open for further replies.

hakihaki

Newbie level 3
Joined
Apr 6, 2009
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,308
Hi

I'd designed VCO using replica current bias(cascode current mirror).

But now I'll design a regulator(load current - 1~2mA) for improvement to VCO phase noise.

I have a question. Which is better VCO phase noise? Is it right that the regulator have VCO phase noise to be better?

Thanks :D
 

mengcy

Member level 5
Joined
Aug 21, 2006
Messages
90
Helped
11
Reputation
22
Reaction score
5
Trophy points
1,288
Location
shanghai
Activity points
1,747
you have nothing to do to improve the VCO phase noise
 

    hakihaki

    Points: 2
    Helpful Answer Positive Rating

vfone

Advanced Member level 5
Joined
Oct 10, 2001
Messages
5,282
Helped
1,549
Reputation
3,099
Reaction score
1,155
Trophy points
1,393
Activity points
33,464
Of course, the bias circuit can influence your VCO phase noise.

There is not a specific rule. A simple bias diode can generate more noise than an integrated regulator using tens of transistors, but also can be in the other way.

The noise generated by the bias circuit depends by its output impedance, by the filtering provided, and by the gain and the noise of the internal components.
 

    hakihaki

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top