Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 module crc_generator #( // width selection parameter parameter crc_poly = 0 // 0: 32-bit, 1: 64-bit // do not modify! calculated parameter parameter width = 32*(1+crc_poly); ) ( output [width-1:0] crc_out ); endmodule
The block symbol looks confusing, what's the purpose of the "input data" ports with different width?
Supporting different a CRC lengths in a single module isn't impossible, but not neccessarily saving resources. It also depends on the topology. Width switching is probably simple in a bit serial (slow) implementation, less useful in a parallel topology.
For choosing the input width, there is a select signal as well.
I tried implementing this by making use of case and assigning crc_out to the individual functions of different widths. It doesnt seem to work though.
Are there any better ways ?
IMO `ifdef should be avoided and parameterized modules should be implemented. The times I've used `ifdef was when the actual number of ports on the module were different and only because I didn't want to end up with a bunch of warnings about unconnected ports.
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I posted (#3) a way to adjust the instantiated width of an output port based on a parameter. It's definitely a better way than putting all the possible options of width on the module, as that method results in a bunch of tool warnings about the unused/unconnected ports.
Do you need all the possible hardware available at all times, so you can switch on the fly in the hardware based on the select signal? I was under the impression from your first post that you just wanted a parameterizable CRC module, which you would set to a specific CRC and instantiate it in a design.Hi!
That works for the output when I am choosing which polynomial width I will be using. It can be parameterized then. But when I am thinking about the inputs coming in (which are of different widths), these inputs depend on the select signal that comes along with them . In this case i will have the hardware for all the different CRC implementation but I am having trouble deciding how to choose the correct hardware based on the select input.
Do you need all the possible hardware available at all times, so you can switch on the fly in the hardware based on the select signal? I was under the impression from your first post that you just wanted a parameterizable CRC module, which you would set to a specific CRC and instantiate it in a design.
So do you need to change the CRC poly during run time? If you don't you should parameterized the input width and change the polynomial select input into a select parameter. You would then use the input width to set the input data width and use a generate to select the CRC polynomial hardware for that instance.
I believe I answered about runtime selectable poly in post #2. You didn't yet tell about implementation details and which problems you experience.
always @(posedge clock or negedge reset) begin
if (!reset) crc_out <= 'd0;
else begin
if (sel == 1'b0)
crc_out <= functCRC8(.data(data8), .crc(crc));
else crc_out <= functCRC16(.data(data16), .crc(crc));
end
function [15:0] functCRC8;
input [7:0] data8;
input [15:0] crc;
......
endfunction
function [15:0] functCRC16;
input [15:0] data16;
input [15:0] crc;
......
endfunction
You are saying that while it is in operation, you will switch between CRCs?The polynomial can be parameterized because I can choose which CRC I wish to implement. But the input data width cannot be parameterized because it comes in along with the select signal and based on the select signal I will pick the particular CRC function. So all of the hardware for the different data widths will have to be present.
You are saying that while it is in operation, you will switch between CRCs?
If so then this design is overly convoluted it would be better to create generic CRC code with the poly, widths, etc all parameterized and then just instantiate all the various CRCs you require in the top level of code and use muxes and demuxes for deciding which CRC you are using at any given time. The amount of logic isn't going to change from your current design and the CRC code itself will be more useful overall.
So what I am dealing with is a lot more convoluted. What you said is working for me when I am choosing between different widths and polynomials. I just use case. So all the hardware is present.
But I have this additional action where a few number of bits are getting added to my data and coming to my crc module. For instance, as i have drawn the figure, the 256 bit data can come as 256+n ; where n is a parameter in the previous module and it will be a parameter in my module as well.
And this 256+n data has a fixed CRC polynomial. So between the 2 cases we know that this data will only be going to the second case.
Now I am being recommended to use `ifdef because apparently it reduces hardware. As the extra data is a parameter it will always be fixed.
How can I make use of `ifdef inside one particular case to choose between the different CRC engines? Just to make it clear; the different widths of data going to this particular CRC polynomial engine will be in my code; I just need to make use of `ifdef to choose from these. Any help will be appreciated.
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