variable input gate in VHDL?

generic-width or gate in vhdl

Is it possible to define an n input logic gate where n is a generic parameter?

Thanx

vhdl or with n inputs

hi
yes u can surely use generic statement in order to make a n- i/p gate.
Below i am putting the Code for a simple N- i/p AND gate.

But i wud suggest u to please go and read some relevent Books like J. Bhasker and Perry for the basiocs as the question u hav asked is a simple basic Question.

library ieee;
use ieee.std_logic_1164.all;
entity gen_and is
generic( N: integer:=2);
port ( a,b : in std_logic;
c : out std_logic);
end entity;

Architecture arch1 of gen_and is

begin
c<=a and b;
end arch1;


entity gen is
end entity;

Architecture arch of gen is

signal ip,op: std_logic;
component
gen_and is
generic( N: integer:=2);
port ( a,b : in std_logic;
c : out std_logic);
end component;

begin
A1: gen_and generic map( 4) port map (ip,op);

end ARCH;

n input or gate using vhdl

The code you posted is not an n-input AND gate buddy, actually it is just a 2-input AND.
You define a generic parameter N but you don't use it, so what's the point?
What I am asking is below...

By the way, I have the two books as hardcopy that you've mentioned, thank you for your advice


i1--------|
i2--------|
i3--------|
.---------| AND ----> F
.---------|
.---------|
in--------|

n-i/p or gate in vhdl

I am sorry
Here is aright code.
I am extremely very sorry for the same.
Kindly see the following code

library ieee;
use ieee.std_logic_1164.all;

entity gen_and is
generic( N: integer:=5);
port ( a : in std_logic_vector( n downto 1);
c : out std_logic);
end entity;

Architecture arch1 of gen_and is

Signal s : std_logic_vector((n+1) downto 1);
begin

s(1)<='1';
g1: for i in 1 to n generate

s(i+1)<=a(i) and s(i);
end generate;
c<=s(n+1);

end arch1;