Re: variable clock generation in verilog using task
I don't get why you generate your clocks with this code.
It's a lot simpler to use a clock module that generates the clock. Then it represents a clock oscillator on a board (the testbench).
I use a generic clock generator module that accepts parameters for either period/frequency, value(either period/frequency), differential/single-ended. It has 2 outputs +/- and 1 input an enable/disable port.
I'd rather write something like the clock generate I use once and never have to write it again, instead of doing what you are doing by adding all that code (a lot of which seems redundant and convoluted) to generate a simple clock at a specific frequency.