Do you want to vary by simulator variable, by circuit voltage,
or what?
I suggest you look at whether veriloga is supported by your
HSPICE version and if so, scrounge for veriloga varactor code
you can modify to suit (or, find a varactor model you like and
just linearize or cal-map the C-V transfer function). If it's a
circuit driven variation you are looking for, and not just a
stepping of a variable.
Do you want to vary by simulator variable, by circuit voltage,
or what?
I suggest you look at whether veriloga is supported by your
HSPICE version and if so, scrounge for veriloga varactor code
you can modify to suit (or, find a varactor model you like and
just linearize or cal-map the C-V transfer function). If it's a
circuit driven variation you are looking for, and not just a
stepping of a variable.
the capacitors in this circuit change by move (capacitive accelerometer ) and Unfortunately i have no information about veriloge
if I understand correctly , i can use veriloge in hspice? how??
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I study a little about verilog model in hspice and find this for resistor model if you can write variable capacitor in verivlog i thank you verrrry much
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*Title: Simple Verilog-A Resistor
.hdl resistor.va
.options post=1
X1 10 resistor r=1
VS 101
.dc VS 0101
.end
The va file:
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// Simple resistor
`include "disciplines.vams"
module resistor(p,n);
parameter R=1.0 from (0:inf);
electrical p,n;
analog I(p,n)<+ V(p,n)/R;
endmodule
In order to simulate the transient response of the readout
circuit, a pair of time-varying sensor capacitors are required.
A simple varactor model is implemented in Verilog-A which
produces a voltage-controlled capacitor. This model has four
terminals, where two terminals are the capacitor terminals, and
the other are the voltage input terminals. The Verilog-A model
is built upon the following equation:
C = C0 + CV Vin (4)
Q = CVC (5)
IC = dQ/dt (6)
This model consists of a fixed capacitor C0, and a variable
capacitor CV . The model takes in a voltage Vin as an input and
provides a variable capacitor C. Note that VC is the voltage
across the capacitor C. In this design, C0 is assumed to be
100 fF, CV is 1 fF, and Vin can be any time-varying voltage
signal that controls the change in the output capacitance
.
i dont know how define and write Vi and c=c0+c1vi equation in verilog-a and use it in hspice