[SOLVED] Values of set/ reset when Instantiating ODDR?

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ankit rajput

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hi,

when we instantiate ODDR then how to provide value to "SRTYPE" and set/reset. I mean for "async" and "sync" in SRTYPE what should be the value in set /reset?
 

dpaul said:
Pg 292 - 294 has port description table and RTL instantiation templates to help you out.
Click to expand...



thanks for quick reply. I have already seen this document. But I don't understand that suppose "SRTYPE" is ASYNC then what should be the values of set and reset?
 

You set the "SRTYPE" to either "SYNC" or "ASYNC" depending on the reset signal used in your design.
E.g. - If you have a sync reset, then the ODDR inst will look something like this(VHDL):

Code: 
        oddr_inst: ODDR
        generic map(
            DDR_CLK_EDGE => "SAME_EDGE",
            INIT         => '0',    -- Initial value for Q port (’1’ or ’0’)
            SRTYPE       => "SYNC"  -- Reset Type ("ASYNC" or "SYNC")        
        )
        port map(
            Q  => txd_o,                           -- o/p data
            C  => clk,                               -- clock
            CE => data_out_enable,          -- enable pin
            D1 => pos_edge_data,           
            D2 => neg_edge_data,
            R  => reset,                           -- sync or async reset 
            S  => '0'
        );

Code snippets are given in the '*InstantiationTemplate', pg 293 and pg 294.
 
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