validation of AES core

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kzirshan

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i am working on implementation of AES on FPGA,i have made it's core and simulate it, now i am interested to check validity of my core after implementation on FPGA. kindly suggest me, that how can i check my core performance after implemented it in FPGA.


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kzirshan
 

I think the performance of the core depends on the maximum clock used by your design. The maximum clock can be calculated by the compiler.
 

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