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Validating PMOS BIAS characteristics

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yefj

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Hello ,I have built a PMOS device with Vt=-0.39 shown in the link bellow
  • Vs=1.8 Vg=-1.5
  • Vgs=-1.5-1.8=-3.3V
  • |Vgs-Vt|=|Vgs-Vt|=|-3.3-(-0.39)|=2.91>|Vds|=1.8
I get a result where no matter what is my Source voltage it will alway be in linear state.
although as you can see in the plot bellow i get a good result.
Where did i go wrong in the biasing condition of PMOS?
Thanks.
1676723624557.png

https://sanjayvidhyadharan.in/Downloads/tsmc_180_nm/tsmc018.lib

1676723051510.png
 

Hello Crutschow ,the problem is with the math conditions.
I got the curve correctly.
 

I showed you how to generate the curves with a negative voltage drain supply in my other post to you.
Why did you not do this simulation the same way?
Vs=1.8 Vg=-1.5
Vgs=-1.5-1.8=-3.3V
|Vgs-Vt|=|Vgs-Vt|=|-3.3-(-0.39)|=2.91>|Vds|=1.8
I get a result where no matter what is my Source voltage it will alway be in linear state.
although as you can see in the plot bellow i get a good result.
Where did i go wrong in the biasing condition of PMOS?
 

I get a result where no matter what is my Source voltage it will alway be in linear state.
although as you can see in the plot bellow i get a good result.
You show a few equations, say there is a problem, then say you get a good result.
So which is it?
Those are contradictory statements so I am confused as to what you mean. :confused:.
What exactly are you expecting (or want) to see?
 

my Vgs-Vt is 2.91 too high its not logical
where did i go wrong?
|Vgs-Vt|=|-3.3-(-0.39)|=2.91>|Vds|=1.8
 

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