vague design question

[barry]

There's probably no simple answer for this, but I'll ask anyway; maybe somebody wrote their PhD thesis on it.

Let's say we have two RAMs in an FPGA. Which will give the best performance:

1) Using two separate address busses, which will utilize more routing resources, but may allow for more efficient placement

or

2) Using a common address bus, which will use fewer routes, but might cause some placement issues.

Any thoughts?

 

[ads-ee]

Barry,

Let me take a stab at this.

From my experience I've done designs with both options.
My criteria for doing either 1 or 2 was:

1) I know the RAMs will be placed in different locations and I've modified code to the point where I know the number of signals going to the RAM+address/control have been reduced to a minimum number of signals, which I've added keep/preserve type attributes to ensure they don't get converted back to option 2.

2) I know RAMs will be located next to each other (because I put them there/verified they are placed that way)

Either way will give similar performance. I've utilized option 1 mostly due to problems with placement and routing congestion.

YMMV

Regards

 

[TrickyDicky]

As has been mentioned in other threads recently - it depends. I think ADS-ee has said as much above, but let me throw an experience of mine in:

I have had infered rams that used the same address bus. In the code they were two separate signals (ie, two seaprate arrays in the VHDL), but because Quartus got clever, figured out the address bus was the same for both, and both arrays together fitted in a single M9k, it merged the two at the map stage. So in the RTL diagram and elaborated heirarchy gave me two separate rams, in the fit report one used 1 m9k and the other used 0, and there was and info output that the two had been merged. With two separate address busses I get the feeling the merge may not have happened (but I didnt try).

 

[ads-ee]

Yeah, I've seen that happen before...and the resulting search for the missing RAM when I tried to add SignalTap and/or Chipscope to the design...then realizing it is now a much larger (wider) single RAM block.

- - - Updated - - -

Also separating the addresses (if they are generated by identical logic) won't help unless the preserve/keep attributes are used. They would also get merged.