V to I converter stability ?

[cmos_ajay]

Hello,
Attached is the circuit which I saw in a paper. Its a power on reset circuit.
In the V to I section of the circuit the stability components Rz and Cz are connected between the supply VDD and the drain of pmos transistor PM7.

* Why is that so ?
* Is it not appropriate to connect them between tha gate of PM7 and drain of PM7 ?

Will appreciate an explanation for the same. Thanks.

 

[gujaratibhai]

hi cmos_ajay,

i agree with your statement Rz+Cz should "connect them between th[e] gate of PM7 and drain of PM7". Cz is the compensation cap and Rz would be the nulling resistor for stability if placed across gate+drain of PM7. I bet this is incorrectly drawing schematic in that paper.

Though I am curious whether we both could be wrong and having Rz+Cz connect to the supply provides some other magical means.

 

[Dominik Przyborowski]

The drain of PM7 is connected to low impedance node (resistor R2 which I assume is in order of several kΩ not more) so PM7 is not a gain stage, so Miller effect does not work there. So to compensate this circuit Rz, Cz network is used to provide pole gout_of_OTA/Cz and LHP zero 1/Cz·Rz.
In addition when You look on the PSRR+ for this circuit it doesn't suffer for high frequency diode connection as it take place in Miller compensated opamps.

 

[shanmei]

Great comment, Dominik Przyborowski.