Using VHDL with Accelerometer ADXL346

[NiamhB90]

Hi,
I'm trying to set up my ADXL 346 with my Xilinx CoolRunner II CPLD. From my understanding of the datasheet I wrote some code in order to simply read the device ID. I am using SPI 4 wire transfer and my code is supposed to tell the ADXL346 to read from the Address 0x00 which should contain the device ID 11100110

The following is the VHDL code I downloaded to my CPLD board. Vdd through a resister divider network powers the device with 1.8 V through Vs and VI/O.
The CPLD outputs the values I want as in Sdi reads 110000000 and yet Sdo doesn't produce anything when tested on an oscilloscope.

please can somebody help me I am at my wits end trying to get this accelerometer to work!

Heres the VHDL code I used:
----------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---------------------------------------------------------------------

entity DeviceID is
PORT( clk: IN STD_LOGIC;
reset,Int1,Int2,Sdo: IN STD_LOGIC;
--X0,X1,Y0,Y1,Z0,Z1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
Vdd,Sclk,CSn,Sdi : OUT STD_LOGIC);

end entity DeviceID;

-----------------------------------------------------------------------

architecture Behavioral of DeviceID is

-----------------------------------------------------------------------
-- first counter reduces the clock speed of the internal 8MHz clock to 125kHz
SIGNAL count_value : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- second counter is for the case statements
SIGNAL count_value2 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL clk_int : STD_LOGIC;

-----------------------------------------------------------------------
---- 8MHZ clock divider
begin

-----------------------------------------------------------------------

count_proc : PROCESS(clk,reset)
BEGIN
IF (reset = '0') THEN
count_value <= "00000000";
ELSIF ( clk'EVENT AND clk = '1') THEN
count_value <= count_value+1;
END IF;
END PROCESS;

-----------------------------------------------------------------------
-- the clock for the case statements to follow should be now 125kHz
clk_int <= count_value(6);


-----------------------------------------------------------------------

count2_proc : PROCESS(clk_int,reset)

BEGIN
Vdd <= '1';
IF (reset = '0') THEN
count_value2 <= "000000000";
ELSIF ( clk_int'EVENT AND clk_int = '1') THEN

-- the If statement means that once the initialisation of the Acc has been done
-- /Cs and Sclk stay high unless program is reset
IF (count_value2 = "000110011") THEN
count_value2 <= "000110011";
ELSE
count_value2 <= count_value2 +1;
END IF;

END IF;

case count_value2 is
-- Set up chip select and clock according to datasheet

when "000000000" => Csn <= '1'; Sdi <= '1'; Sclk <= '1';--0
when "000000001" => Csn <= '0'; Sdi <= '1'; Sclk <= '1';--1
when "000000010" => Csn <= '0'; Sdi <= '1'; Sclk <= '0';--2
-- R
when "000000011" => Csn <= '0'; Sdi <= '1'; Sclk <= '0';--3
when "000000100" => Csn <= '0'; Sdi <= '1'; Sclk <= '1';--4
when "000000101" => Csn <= '0'; Sdi <= '1'; Sclk <= '0';--5
-- MB
when "000000110" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--6
when "000000111" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --7
when "000001000" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--8
-- A5
when "000001001" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--9
when "000001010" => Csn <= '0'; Sdi <= '0'; Sclk <= '1';--10
when "000001011" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--11
-- A4
when "000001100" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--12
when "000001101" => Csn <= '0'; Sdi <= '0'; Sclk <= '1';--13
when "000001110" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--14
-- A3
when "000001111" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--15
when "000010000" => Csn <= '0'; Sdi <= '0'; Sclk <= '1';--16
when "000010001" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--17
-- A2
when "000010010" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--18
when "000010011" => Csn <= '0'; Sdi <= '0'; Sclk <= '1';--19
when "000010100" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--20
-- A1
when "000010101" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--21
when "000010110" => Csn <= '0'; Sdi <= '0'; Sclk <= '1';--22
when "000010111" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--23
-- A0
when "000011000" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--24
when "000011001" => Csn <= '0'; Sdi <= '0'; Sclk <= '1';--25
when "000011010" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --26
-- D7
when "000011011" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --27
when "000011100" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --28
when "000011101" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --29
-- D6
when "000011110" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --30
when "000011111" => Csn <= '0'; Sdi <= '0'; Sclk <= '1';--31
when "000100000" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --32
-- D5
when "000100001" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --33
when "000100010" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --34
when "000100011" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--35
-- D4
when "000100100" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --36
when "000100101" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --37
when "000100110" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --38
-- D3
when "000100111" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --39
when "000101000" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --40
when "000101001" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --41
-- D2
when "000101010" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --42
when "000101011" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --43
when "000101100" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --44
-- D1
when "000101101" => Csn <= '0'; Sdi <= '0'; Sclk <= '0';--45
when "000101110" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --46
when "000101111" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --47
-- D0
when "000110000" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --48
when "000110001" => Csn <= '0'; Sdi <= '0'; Sclk <= '1'; --49
when "000110010" => Csn <= '0'; Sdi <= '0'; Sclk <= '0'; --50
when others => Csn <= '1'; Sdi <= '0'; Sclk <= '1';
--------------------------------

end case;
end process;

end Behavioral;

--------------------------------------------------

 

[joelby]

Try simulating it and look at the waveform - this might make what is happening a bit easier to visualise!

A few comments:
- Your SCLK clock appear to have a 33% duty cycle, which might not matter but is a bit strange.
- In the very first state, your accelerometer may not receive the first '1' because you drive Sdi and Sclk high at the same time. Perhaps you meant to make Sclk low in the first state? Your tHOLD will be violated for this first bit.
- The counter may kick off as soon as the CPLD fires up if reset is low. I usually like to have a start up delay to allow peripheral chips to fully initialise. Refer to the data sheet to see if there is one, or play it safe with a delay.

 

[NiamhB90]

I have simulated it and it works fine when simulated. It is once it is downloaded onto the board and hooked up to the accelerometer,the accelerometer doesn't work. What do you mean by 33% duty cycle? The first three counts incorporate the delay according to the datasheet, the photo attached is how I figured out the count.

 

[TrickyDicky]

33% duty cycle means that the clock is high for 33% of the time and low for 66% of the time. This might be a reason why it isnt working. IS there any reason you did this and not a 50% duty cycle?

 

[joelby]

How do you know it works fine when simulated? Have you got a simulation model of the ADXL346?

Let us know how you go after fixing the three things suggested!