I am not sure what you are intent to do.
First of all, Verilog/VHDL mixed projects depend heavily on the support of the tools you use. Check the manual of your tools (Quatus) can find out the name convertion between these two languages.
The second thing you need to understand, only part of the name spaces are recognizable between languages.
For example, VHDL, under the support of your tools, can recognize the module name, port and port width of a verilog module but have no idea what is inside.
Verilog, on the other hand, can recognize the entity name, ports (defined by std_logic or std_logic_vector in most cases), but have no idea what is inside and which architecture should be used when initialize an entity (this is defined by the tool).
If the variable mentioned in your question is really a variable in a verilog code, I am afraid to say there is no way for a VHDL entity to visit it, only if your tool manual say otherwise. In fact, it is already quite unlikely for a VHDL to visit any internal signal (no matter reg or wire) in a verilog module unless it is connected with a port.
May be a solution for you, output any internal signals you need to a port and therefore the VHDL entity can visit it.
After all, direct access a variable in a verilog module using hierarchical names is not recommended in RTL coding. This is only a useful trick in test benches.