using vhdl & verilog in same project

[grules]

iam trying to use to code files: VHDL and Verilog in same project using quartus. I get error that variables that i have in verilog not defined in vhdl.
How can i use both files in same project?
thanx!

 

[ckshivaram]

check this
New Project Wizard ? Project Settings Page

---------- Post added at 10:52 ---------- Previous post was at 10:49 ----------

check this discussion
https://www.edaboard.com/threads/82294/
**broken link removed**

and these links

SystemVerilog DPI Tutorial: Page 1

 

[grules]

Hi
i still have some problems..
I created a new project in Quartus , added two files to project, one is VHDL second is Verilog file, compilation is OK, but what i need is to use one of the variable (its bit string that i got from UART port) from Verilog code and USE it in VHDL code to controll my fpga in way that i need ( turn on LEDs for example).

So far after compilation i doing Pin Planner and i see only I/O from VHDL code ,Where is Verilog I/O in Pin planner??
If I'll run Verilog file in separate project it will run good and Pin Planner is recognize all I/O ports.

So still I didnt find a way to combine to codes in same project and use both codes I/O ports in Pin Planner.

thanx!

 

[wsong0210]

I am not sure what you are intent to do.
First of all, Verilog/VHDL mixed projects depend heavily on the support of the tools you use. Check the manual of your tools (Quatus) can find out the name convertion between these two languages.
The second thing you need to understand, only part of the name spaces are recognizable between languages.
For example, VHDL, under the support of your tools, can recognize the module name, port and port width of a verilog module but have no idea what is inside.
Verilog, on the other hand, can recognize the entity name, ports (defined by std_logic or std_logic_vector in most cases), but have no idea what is inside and which architecture should be used when initialize an entity (this is defined by the tool).

If the variable mentioned in your question is really a variable in a verilog code, I am afraid to say there is no way for a VHDL entity to visit it, only if your tool manual say otherwise. In fact, it is already quite unlikely for a VHDL to visit any internal signal (no matter reg or wire) in a verilog module unless it is connected with a port.

May be a solution for you, output any internal signals you need to a port and therefore the VHDL entity can visit it.
After all, direct access a variable in a verilog module using hierarchical names is not recommended in RTL coding. This is only a useful trick in test benches.

 

[grules]

FINALLY !!! ITS WORKS! :razz:
So my mistake was that i didn't declare the COMPONENT (that in my case is verilog file) right.
so the right way is : first i write COMPONENT and his ports ( in architecture) then i need to do PORT MAPPING (ports from verilog file).