Using Verilog/VHDL with HSPICE?

[dnanar]

Hi,

I'm looking for a way to convert a Behavorial description (in VHDL or VERILOG) into a (H)SPICE netlist. I did it in the past with tools from Cadence, but in my current situation I can only use tools from Synopsys.

I've tried to look into Design Compiler / Nanosim but I couldn't find anyway of doing that. Is there any other software to do this please? Or did I miss something with these tools?

Thanks.

 

[FvM]

Simulating a digital circuit in an analog simulator only makes sense if you have a transistor level description of your synthesized logic along with technology files, e.g. in an ASIC design tool. I suppose you don't have it in synopsis, so what do you expect from a SPICE simulation?

 

[dnanar]

My problem is that I have an analog circuit (in the form of an HSPICE netlist) that monitors some parameters of my digital circuit (in my case the drop in the supply current caused by the computation of the digital circuit). I made a SPICE simulation with some simple digital circuits, but now I want to simulate more complex one.

What do you think is the best way to do that? I agree that at some point I'll have to get a transistor level description of my synthesized logic, and I thought synopsys provided those files in their library for "University program" ( **broken link removed** ). Did I misunderstood something please?

Thanks.

 

[jbeniston]

Use Design Compiler to synthesize the Verilog RTL into a Verilog gate-level netlist.

Then you can import the Verilog netlist into Synopsys Custom Designer, if you have it, and simulate through that.

If not, providing you have the transistor levels models for the standard cells, you should be able to simulate with that. You will just need to use a netlisting program to create a spice netlist from the gate-level Verilog. Something like v2lvs, nettran etc. Depends what other tools you have.