Using the Xilinx Memory Endpoint Test (MET), how can I change the start address??

[minho_ha]

Hi, I'm trying to use MET driver for checking the signal between host PC (linux OS, ubuntu) and FPGA BRAM.

System is consist of 'PCIe - AXI - BRAM controller - BRAM'. (All IPs are presented by Xilinx Vivado)

I succeeded in changing the data when read and write.

And now, I wanna change the start address. For example, for now, read and write operation start with 0 address of BRAM (in hex, 0x000 and PCIe BAR 0x80000000). But I wanna start write operation from 10th address of BRAM (in hex, 0x00A).

How can I solve the above problem?

 

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How can I solve the above problem?

Usually this involves tracing address generation code back through the design...or is that the point of this post you want someone else to do this for you?

 

[minho_ha]

Usually this involves tracing address generation code back through the design...or is that the point of this post you want someone else to do this for you?

I just wanna get advice from the one who used MET driver before.