Hi, I'm trying to use MET driver for checking the signal between host PC (linux OS, ubuntu) and FPGA BRAM.
System is consist of 'PCIe - AXI - BRAM controller - BRAM'. (All IPs are presented by Xilinx Vivado)
I succeeded in changing the data when read and write.
And now, I wanna change the start address. For example, for now, read and write operation start with 0 address of BRAM (in hex, 0x000 and PCIe BAR 0x80000000). But I wanna start write operation from 10th address of BRAM (in hex, 0x00A).
How can I solve the above problem?