It's unconstrained to keep the design generic...
X is an array entity port not an internal signal - therefore, it must be defined externally in a package. Can't use generics...
Re: Using the "others" statement on an unconstrained VHDL 2008 array port
two options:
1. x <= (x'range => (x(x'low)'range => '0'));
2. or use a set procedure:
Code:
package pack is
type a_t is array(natural range <>) of std_logic_vector;
procedure setall( signal x : out a_t;
constant v : std_logic := '0');
end package pack;
package body pack is
procedure setall( signal x : out a_t;
constant v : std_logic := '0') is
begin
for i in x'range loop
for j in x(i)'range loop
x(i)(j) <= v;
end loop;
end loop;
end procedure;
end package body;
....
setall(x, '0');
VHDL 93 (maybe 87, but Im not sure, and probably not) allows you to have unconstrained ports. This allows the connected signal to set the size of the port.
It does mean you have to use the attributes of the port to set other arrays internally, rather than the generic.
I dont understand why MR shaiko cannot use a couple of generics though. There is no situation where I could not use them for this setup.