Using the "others" statement on an unconstrained VHDL 2008 array port

[shaiko]

Signal x is defined as an unconstrained array output port.
Somewhere in my design, I want to reset all the array elements.

I tried using:

x <= ( others => ( others => '0' ) ) ;

Compilation fails with the following error:

OTHERS choice cannot be used in unconstrained array aggregate

Any idea how I can work around the problem and still leave the array port unconstrained ?

 

[barry]

I think your output port needs a dimension. Why do you want it unconstrained? Maybe you should use a GENERIC.

 

[shaiko]

It's unconstrained to keep the design generic...
X is an array entity port not an internal signal - therefore, it must be defined externally in a package. Can't use generics...

 

[verylsi]

I have used Generics in entity ports, and it works fine for me.
But I am not sure about vhdl 2008

 

[TrickyDicky]

Re: Using the "others" statement on an unconstrained VHDL 2008 array port

two options:

1. x <= (x'range => (x(x'low)'range => '0'));

2. or use a set procedure:

package pack is 
    type a_t is array(natural range <>) of std_logic_vector;
    
    procedure setall( signal   x : out a_t;
                      constant v : std_logic := '0');
end package pack;

package body pack is
    procedure setall( signal   x : out a_t;
                      constant v : std_logic := '0') is
    begin
        for i in x'range loop
            for j in x(i)'range loop
                x(i)(j) <= v;
            end loop;
        end loop;
    end procedure;
end package body;

....

setall(x, '0');

- - - Updated - - -

I think your output port needs a dimension. Why do you want it unconstrained? Maybe you should use a GENERIC.

VHDL 93 (maybe 87, but Im not sure, and probably not) allows you to have unconstrained ports. This allows the connected signal to set the size of the port.
It does mean you have to use the attributes of the port to set other arrays internally, rather than the generic.

I dont understand why MR shaiko cannot use a couple of generics though. There is no situation where I could not use them for this setup.

 

[shaiko]

I dont understand why MR shaiko cannot use a couple of generics though. There is no situation where I could not use them for this setup.

How??
the type of x is defined in a package as follows:

type array_port is array ( natural range <> ) of std_logic_vector ; -- this type is an unconstrained array

x is declared as an entity port as follows:

x : in array_port ;

How can I set the boundries of x with generics when declaring it in the entity?

 

[TrickyDicky]

assuming generics of D and W:

x : in array_port(D-1 downto 0)(W-1 downto 0);

 

[shaiko]

Much obliged.