using the dual port ram of latticee xp2 in VHDL

[Sarvjeet Verma]

Can anyone guide me to use the dual port RAM in the lattice XP2 FPGA as I have followed the memory guide and hae completed the creation of the Dual port RAM file(DP16KB which is the component) and now when I make my module and try to port map with the created file I am finding that the output data signal is not taking any load.

 

[lucbra]

Diamond creates a template VHD file that you can use in your design. This file ends with _tmpl.vhd.

It shouldn't be that difficult to implement. I strongly recommend to read the extended datasheet of the XP2. Some of the blocks use active low reset, but I'm not sure if this is the case for the DPRAM.