That means SPi Master and SPI Slave can be used as soft components on the same board and they can be tested by sending data from Master to slave?
1.But if SPI master is in one development board then SPI slave should be external to the board I guess(Correct me if I am wrong).
I have made one development board as Slave now...to test the functionality I thought another dev board is required as master.....as I dont have another development board with me to test its functionality...
If both can be tested on the same board then my work of testing will be easier.......Please clear me......
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 // master interface output MSTR_MOSI_PIN, output MSTR_SCLK_PIN, output MSTR_SS_N_PIN, input MSTR_MISO_PIN, // slave interface input SLV_MOSI_PIN, input SLV_SCLK_PIN, input SLV_SS_N_PIN, output SLV_MISO_PIN
One of your problems is you were supposed to hook up the master and slave to PINS on the FPGA not use wire.
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Then hook up wires on the part between the *_MOSI_PIN, *_SLCK_PIN, etc. You also need to have a circuit to produce the master side wishbone signals.
And when you do test with 1 board, obviously make sure that you DO go outside fpga with the SPI signals. Have pins for both the spi master and for the spi slave, and physically connect those pins. Possibly with a series resistor.
Being too lazy to look it up myself...is OSCF some sort of internal clock generator in Lattice? Is it some sort of generated clock output off a crystal hooked up to pins on the device?
One of your problems is you were supposed to hook up the master and slave to PINS on the FPGA not use wire.
something like:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 // master interface output MSTR_MOSI_PIN, output MSTR_SCLK_PIN, output MSTR_SS_N_PIN, input MSTR_MISO_PIN, // slave interface input SLV_MOSI_PIN, input SLV_SCLK_PIN, input SLV_SS_N_PIN, output SLV_MISO_PIN
Then hook up wires on the part between the *_MOSI_PIN, *_SLCK_PIN, etc. You also need to have a circuit to produce the master side wishbone signals.
Currently what you have isn't even complete, most of the code doesn't even look to be hooked up to the top level ports. It's no wonder you're missing logic after synthesis. Did you do any up front design work before writing code? Like coming up with a block diagram? The code you posted looks like something just hacked together with absolutely no thought behind it.
Regards,
will check out by adding the signals to the top module
Be sure to also add solder blobs to the top level module.
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