Using SPI Slave component

[Tan]

I have designed SPI Slave on lattice Mico and connected leds.
Can anyone please give me idea how to test that slave alone as I dont have anyother board with me to make it as master and connect it to my slave.Please....I am stuck ...

 

[shihab_leo]

hi,
you can make an SPI master in the same Micro (i am not familiar with lattice, maybe it has some built-in SPI master. if not you can make a soft SPI using bit banging) and connect SPI master pins externally to SPI slave pins. Now send some data through SPI master and analyze the data received by SPI slave.

 

[mrflibble]

Two solution spring to mind:

1 - as shihab_leo suggests, implement both a master and slave one the board you have.
2 - grab whatever mcu dev board you have lying around, and use that as spi master. If you don't have one, get an stm32f4 or msp430 board or something. These are dirt cheap.

 

[Tan]

That means SPi Master and SPI Slave can be used as soft components on the same board and they can be tested by sending data from Master to slave?

1.But if SPI master is in one development board then SPI slave should be external to the board I guess(Correct me if I am wrong).

I have made one development board as Slave now...to test the functionality I thought another dev board is required as master.....as I dont have another development board with me to test its functionality...

If both can be tested on the same board then my work of testing will be easier.......Please clear me......

 

[mrflibble]

That means SPi Master and SPI Slave can be used as soft components on the same board and they can be tested by sending data from Master to slave?

Sure, why not.

1.But if SPI master is in one development board then SPI slave should be external to the board I guess(Correct me if I am wrong).

Why should it. You are the one deciding what you want to test.... Obviously it does have advantages to test it against an external board. But IFF you say that 1) you don't have an external board and 2) you want to test the SPI slave, then have fun working out a Venn diagram of possible test scenarios and see what you end up with.

I have made one development board as Slave now...to test the functionality I thought another dev board is required as master.....as I dont have another development board with me to test its functionality...

If both can be tested on the same board then my work of testing will be easier.......Please clear me......

Best scenario: use two seperate boards. Backup plan for those that only have 1 board: make do with 1 board. Seems engineering 101 to me really. What do you want to do? What do you have available. Make do.

And when you do test with 1 board, obviously make sure that you DO go outside fpga with the SPI signals. Have pins for both the spi master and for the spi slave, and physically connect those pins. Possibly with a series resistor.

 

[Tan]

Hey Thanks alot...
WIll try that immediately....I cannot wait to test my Master and Slave on the same board.....Thanks again....

 

[mrflibble]

Oh yeah, quick tip. If your board happens to have two clock sources, then try to use one clock for the master and the other for the slave. Or use the clock source from another board you have lying around.

If you use a single clock source for both master & slave, your test results will be a bit optimistic. Because your synchronizers will be extremely synchronous.

 

[Tan]

Not working :-(

 

[mrflibble]

Testbench time?

 

[Tan]

Hi,
I have designed SPI Slave in one development board(using soft core) and need to check(As i mentioned).There is no SPI master to check.
1.I have tried taking the code from Opencores.org and instaiate it.It is giving lot of errors.

when I instatiated I could took only two signals in the top file(reset and some leds)
when I tried to give pin assignment I could not find reset pin in the pin constraint I found only gpio pins.

2.Can I test it using oscilloscope.
Please help me i know this is very small protocol,but testing is creating issues for me...

The above mentioned answers did not work as spi master and slave should be placed in two different boards.
please help me out

below is the code

module TOP(
input wire reset_n,
output [7:0]leds
);

wire clk;
wire [31:0]SPI_DAT_O;
wire clk_i;
OSCF OSCinst0 (.OSC(clk_i));
defparam OSCinst0.NOM_FREQ = "26" ;

wire SPI_SLAVEMISO_SLAVE;
wire SPI_SLAVEMOSI_SLAVE;
wire SPI_SLAVESS_N_SLAVE;
wire SPI_SLAVESCLK_SLAVE;

wire wb_adr_i;
wire wb_dat_i=32'h0AA0;
wire wb_dat_o;
wire wb_sel_i;
wire wb_we_i;
wire wb_stb_i;
wire wb_cyc_i;
wire wb_ack_o;
wire wb_err_o;
wire wb_int_o;

slave_msb slave_msb_u (
.clk_i(clk_i),
.reset_n(reset_n)
, .SPI_SLAVEMISO_SLAVE(SPI_SLAVEMISO_SLAVE) //
, .SPI_SLAVEMOSI_SLAVE(SPI_SLAVEMOSI_SLAVE) //
, .SPI_SLAVESS_N_SLAVE(SPI_SLAVESS_N_SLAVE) //
, .SPI_SLAVESCLK_SLAVE(SPI_SLAVESCLK_SLAVE) //

);
spi_top Master
(
// Wishbone signals
.wb_clk_i(clk_i)
,.wb_rst_i(reset_n)
,.wb_adr_i(wb_adr_i)
,.wb_dat_i(wb_dat_i)
,.wb_dat_o(wb_dat_o)
,.wb_sel_i(wb_sel_i)
,.wb_we_i(wb_we_i)
,.wb_stb_i(wb_stb_i)
,.wb_cyc_i(wb_cyc_i)
,.wb_ack_o(wb_ack_o)
,.wb_err_o(wb_err_o)
,.wb_int_o(wb_int_o),

// SPI signals
.ss_pad_o(SPI_SLAVESS_N_SLAVE)
,.sclk_pad_o(SPI_SLAVESCLK_SLAVE)
,.mosi_pad_o(SPI_SLAVEMOSI_SLAVE)
,.miso_pad_i(SPI_SLAVEMISO_SLAVE)
);


endmodule


And I have to activate the master by giving inputs to master so that serial clock is produced and I can test my slave part....

 

[ads-ee]

Being too lazy to look it up myself...is OSCF some sort of internal clock generator in Lattice? Is it some sort of generated clock output off a crystal hooked up to pins on the device?

One of your problems is you were supposed to hook up the master and slave to PINS on the FPGA not use wire.
something like:

---

Code Verilog - [expand]
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// master interface
output  MSTR_MOSI_PIN,
output  MSTR_SCLK_PIN,
output  MSTR_SS_N_PIN,
input   MSTR_MISO_PIN,
// slave interface
input   SLV_MOSI_PIN,
input   SLV_SCLK_PIN,
input   SLV_SS_N_PIN,
output  SLV_MISO_PIN

---

Then hook up wires on the part between the *_MOSI_PIN, *_SLCK_PIN, etc. You also need to have a circuit to produce the master side wishbone signals.

Currently what you have isn't even complete, most of the code doesn't even look to be hooked up to the top level ports. It's no wonder you're missing logic after synthesis. Did you do any up front design work before writing code? Like coming up with a block diagram? The code you posted looks like something just hacked together with absolutely no thought behind it.

Regards,

 

[mrflibble]

One of your problems is you were supposed to hook up the master and slave to PINS on the FPGA not use wire.

...

Then hook up wires on the part between the *_MOSI_PIN, *_SLCK_PIN, etc. You also need to have a circuit to produce the master side wishbone signals.

That would indeed be the idea, as per this quote:

And when you do test with 1 board, obviously make sure that you DO go outside fpga with the SPI signals. Have pins for both the spi master and for the spi slave, and physically connect those pins. Possibly with a series resistor.

So make sure you connect those 8 signals ads-ee listed to 8 physical fpga pins. And then wire up the appropriate connections using physical wires and physical resistors with a physical soldering iron.

 

[Tan]

Being too lazy to look it up myself...is OSCF some sort of internal clock generator in Lattice? Is it some sort of generated clock output off a crystal hooked up to pins on the device?

One of your problems is you were supposed to hook up the master and slave to PINS on the FPGA not use wire.
something like:

---

Code Verilog - [expand]
1
2
3
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// master interface
output  MSTR_MOSI_PIN,
output  MSTR_SCLK_PIN,
output  MSTR_SS_N_PIN,
input   MSTR_MISO_PIN,
// slave interface
input   SLV_MOSI_PIN,
input   SLV_SCLK_PIN,
input   SLV_SS_N_PIN,
output  SLV_MISO_PIN

---

Then hook up wires on the part between the *_MOSI_PIN, *_SLCK_PIN, etc. You also need to have a circuit to produce the master side wishbone signals.

Currently what you have isn't even complete, most of the code doesn't even look to be hooked up to the top level ports. It's no wonder you're missing logic after synthesis. Did you do any up front design work before writing code? Like coming up with a block diagram? The code you posted looks like something just hacked together with absolutely no thought behind it.

Regards,

1. Yes that is the internal oscillator.....
2.Actually...Yes I need to write the wishbone logic..to initiate the transfer..
3." Did you do any up front design work before writing code? Like coming up with a block diagram? The code you posted looks like something just hacked together with absolutely no thought behind it."


My issue is test the Slave spi and send data to LEDS connected to the SPI SLave.......
I have taken the Master code from opencores.org and connected it to the slave generated in the EDK(Lattice MICO).
There is absolutely no chance of doing things "without any thought" I guess as it is very clear that data should e initiated from the master and sent it to slave.

will check out by adding the signals to the top module

thank you for your feedback

 

[mrflibble]

will check out by adding the signals to the top module

Be sure to also add solder blobs to the top level module.

 

[Tan]

Be sure to also add solder blobs to the top level module.

What are solder blobs...I have just taken simple wires and connected to the gpio's on the board.....

 

[mrflibble]

That should be fine too.