module Top_Level( i_clk,
reset,
i_addr,
i_data,
Led_Show
);
// Input to the system
input i_clk;
input reset;
input i_data;
input i_addr;
output Led_Show;
// Data type declarations
wire i_clk;
wire reset;
wire i_data;
wire i_addr;
wire Led_Show;
//Intermediate connections
wire transmit;
wire mosi;
wire miso;
wire sclk;
wire chip_sel;
wire pattern_det;
// SPI state machine
parameter IDLE = 2'b00; // do nothing stage
parameter READ = 2'b01; // Read from the initialized memory block
parameter TRASMIT_FRAME = 2'b10; // Transmit the frame you read
parameter PATTERN_SEARCH = 2'b11; // At the receiving end of slave, search through to see if it matches our dsesire frame.
//Store the current state of the FSM.
reg [1:0] spi_state;
//Pattern to search for in recieved data
parameter pattern = 8'b00110101;
//Instantiate all the modules
//Slaves
SRAM_mem U1( .i_clk(i_clk), //Memeory
.i_addr(i_addr),
.i_data(i_data),
.o_data(transmit)
);
Master_TX U2( .i_Clk(i_clk), //Transmitter
.i_Rst_L(reset),
.i_TX_Byte(transmit),
.SCLK(sclk),
.MOSI(mosi),
.MISO(miso),
.SS(chip_sel)
);
Slave_RX U3( .i_Clk(i_clk), // Receiver
.i_Rst_L(reset),
.SCLK(sclk),
.MOSI(mosi),
.SS(chip_sel),
.MISO(miso),
.o_RX_Byte(pattern_det)
);
Pattern_Search U4( .clk(i_clk), // Pattern Search
.rst(reset),
.in(pattern_det),
.out(Led_Show)
);
// State Machine to control everything goes here
always@(posedge i_clk or negedge reset)
if(!reset) begin
spi_state <= IDLE;
end else
begin
case(spi_state)
IDLE: begin
if(!i_write)
spi_state <= READ;
else
spi_state <= IDLE;
end
READ: begin
if()
transmit <= o_data
endmodule