Using SPI master to read from SRAM to SPI slave.

[Freddy_]

Hello everyone, I need help figuring this out. I am working on a project which involves SPI communication protocols.

The specifications of the project are.

1. I should have an SRAM initialized with data.
2. An SPI master (Transmitter), should be able to read some data from the SRAM, and send it to the Slave.
3. The Slave on the other hand will just send data back to master.
4. At the slave's receive end, I should have a pattern search block to look through the received data, if it matches what I want.

I have designed, the SRAM, the master, slave and the pattern search, but my problem is connecting all of them together, to perform the desired specifications.

I have instantiated all these modules in a top module as show. But I am not sure what to do to get data to move from the SRAM to the master, and to the slave. and finally, to be able to search through.

I am showing the code of my top module here.

module Top_Level( i_clk,
                  reset,
                  i_addr,
                  i_data,
                  Led_Show
                );

// Input to the system
input i_clk;
input  reset;
input i_data;
input i_addr;
output Led_Show;

// Data type declarations
wire i_clk;
wire  reset;
wire i_data;
wire i_addr;
wire Led_Show;

//Intermediate connections
wire transmit;
wire mosi;
wire miso;
wire sclk;
wire chip_sel;
wire pattern_det;

// SPI  state machine
parameter IDLE = 2'b00; //  do nothing stage
parameter READ = 2'b01; // Read from the initialized memory block
parameter TRASMIT_FRAME = 2'b10; // Transmit the frame you read
parameter PATTERN_SEARCH = 2'b11; // At the receiving end of slave, search through to see if it matches our dsesire frame.

//Store the current state of the FSM.
reg [1:0] spi_state;

//Pattern to search for in recieved data
parameter pattern  = 8'b00110101;

//Instantiate all the modules
//Slaves
SRAM_mem U1(            .i_clk(i_clk), //Memeory
                        .i_addr(i_addr),
                        .i_data(i_data),
                        .o_data(transmit)
);

Master_TX U2(           .i_Clk(i_clk), //Transmitter
                        .i_Rst_L(reset),
                        .i_TX_Byte(transmit),
                        .SCLK(sclk),
                        .MOSI(mosi),
                        .MISO(miso),
                        .SS(chip_sel)
);

Slave_RX U3(    .i_Clk(i_clk), // Receiver
                        .i_Rst_L(reset),
                        .SCLK(sclk),
                        .MOSI(mosi),
                        .SS(chip_sel),
                        .MISO(miso),
                        .o_RX_Byte(pattern_det)                     
);

Pattern_Search U4(      .clk(i_clk),  // Pattern Search
                        .rst(reset),
                        .in(pattern_det),
                        .out(Led_Show)
                  
                      

);

// State Machine to control everything goes here

always@(posedge i_clk  or  negedge reset)
        if(!reset) begin
               spi_state <= IDLE;
        end else
             begin
               case(spi_state)
                    IDLE: begin
                           if(!i_write)
                      spi_state <= READ;
                          else
                      spi_state <= IDLE;
               end
              
                     READ: begin
                            if()
                            transmit <= o_data
                  
endmodule

I have tried designing an FSM to make everything work together at this point. But I am stuck on getting the SPI master to read data from the SRAM to the slave and later use the pattern search to detect the pattern.

Any idea of how I could do this would be very helpful.

 

[KlausST]

Hi,

It's rather confusing for me.

From what I understand:
* you need to write code for a PLD
* this PLD is connected to SRAM

It's not clear:
* how many SPI interfaces there are, what speed they use, whether there are multiple devices on one SPI.

*******

2. An SPI master (Transmitter), should be able to read some data from the SRAM, and send it to the Slave.

This sounds as if the SRAM is connected via SPI, but your code does not use SPI to communicate with the SRAM

3. The Slave on the other hand will just send data back to master.

I don't know what this means. "Just send back" sounds like one direction only: slave to master, but in 2) you wrote about: master to slave.
And somehow it sounds to me as a data_stream. But an SPI is not meant as a "streaming interface" because it can't detect/correct framing errors.

4. At the slave's receive end, I should have a pattern search block to look through the received data, if it matches what I want.

This sounds like you want write additional code for a SPI_slave_device. But in your code you have both in one PLD.
I'm really confused.

***
You talk about SPI_read and SPI_write. (Also in the code as SPI states).
Now SPI is a bidirectional interface, which means it writes (Master to slave) at the same time as it reads (slave to master).
So the difference is just whether you discard the received data or not. I see no need to differ between read and write on an SPI master.

So I wonder when you say "read and write" whether you talk about the SPI hardware interface, or f you are talking about the protocol (meaning of the transferred data).


****
I recommend to draw a sketch that shows how many PLDs there are, how many interfaces there are, how many devices there are at each interface.

Klaus

 

[FvM]

There's no physical SPI at the top module interface, thus no hardware SPI. Is it a test bench?

 

[Freddy_]

PLD.

Hi,

It's rather confusing for me.

From what I understand:
* you need to write code for a PLD
* this PLD is connected to SRAM

It's not clear:
* how many SPI interfaces there are, what speed they use, whether there are multiple devices on one SPI.

*******

This sounds as if the SRAM is connected via SPI, but your code does not use SPI to communicate with the SRAM

I don't know what this means. "Just send back" sounds like one direction only: slave to master, but in 2) you wrote about: master to slave.
And somehow it sounds to me as a data_stream. But an SPI is not meant as a "streaming interface" because it can't detect/correct framing errors.


This sounds like you want write additional code for a SPI_slave_device. But in your code you have both in one PLD.
I'm really confused.

***
You talk about SPI_read and SPI_write. (Also in the code as SPI states).
Now SPI is a bidirectional interface, which means it writes (Master to slave) at the same time as it reads (slave to master).
So the difference is just whether you discard the received data or not. I see no need to differ between read and write on an SPI master.

So I wonder when you say "read and write" whether you talk about the SPI hardware interface, or f you are talking about the protocol (meaning of the transferred data).


****
I recommend to draw a sketch that shows how many PLDs there are, how many interfaces there are, how many devices there are at each interface.

Klaus

Okay thank you.