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Using ROM to store/read data coming an audio codec and read it from ROM in VHDL

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ramili

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Hi All,

I'm using DE2 FPGA to play something from a microphone pass it through DE2, do some filtering and play it back through de2. So far, I was successful on playing mic back from speakers.
Now I'm trying to apply a filter to my samples coming from the mic. I have some ideas on how it suppose to work, but I'm not familiar on how to use the ROM for storing the data and reading it back.
I need to store some samples coming from mic into the rom, say like 4 samples, then I'm going to apply an FIR filter and pass those data back to another array, play it back when I got 4 samples on my second array. I basically need a counter to go through these arrays.
Here's what I got for this part so far, it's not complete and it has syntax errors, I'm not really sure how to go on from here. I'm not sure what addresses to choose, and how to use my counter to move through these addresses.

ARCHITECTURE Behavorial OF sram IS
signal count : std_logic;


begin
counting : process(clk, adc_full)
begin
count <= '0';
if (rising_edge(clk)) then
if (adc_full = '1') then
count <= count + '1';
end if;
end if;
end process;


type rom_type is array (0 to 15) of std_logic_vector(7 downto 0);

constant ADC_array : rom_type :=
( 0 => "00010000",
1 => "00010001",
2 => "00010010",
3 => "00010011",
4 => "00010100",
5 => "00010101",
6 => "00010110",
7 => "00010111");

begin
process (count)
begin
case count is
when "0000" => data <= ADC_array(0);
when "0001" => data <= ADC_array(1);
when "0010" => data <= ADC_array(2);
when "0011" => data <= ADC_array(3);
when "0100" => data <= ADC_array(4);
when "0101" => data <= ADC_array(5);
when "0110" => data <= ADC_array(6);
when "0111" => data <= ADC_array(7);
when others => data <= "00000000";
end case;
end process;
 

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