using port arrays in process block

[Richard Divakar Vemagiri]

declaring port as array

Hi,
plz help me with this..

entity fft is
port(input: in array(0 to 7) of integer);
end fft;

Error - near "array": expecting STRING or IDENTIFIER or << or '('

I'm not able to understand wat i should modify.. plz do let me know...

 

[permute]

you need to declare a type. preferably within a package. eg: type my_input_type is array (natural range <>) of integer; if this is in a package, then you can include the package in every file that instantiates or defines fft.

 

[Richard Divakar Vemagiri]

hi permute,
sorry for getting back late. but thank you for ur reply. In fact, i wasn't clear about how u wanted me to do that package stuff. Can u just tell me how to write a package block, and where i should place it in the text editor? Sorry, but I'm new to VHDL and im' trying to learn...
Thanking You,
Richard.

you need to declare a type. preferably within a package. eg: type my_input_type is array (natural range <>) of integer; if this is in a package, then you can include the package in every file that instantiates or defines fft.

 

[mrflibble]

... Sorry, but I'm new to VHDL and im' trying to learn...

Asic-world as some pretty good VHDL tutorials.

Hope that helps you on your way!

 

[Richard Divakar Vemagiri]

package pck is
type my_input_type is array(0 to 7) of integer;
end pck;
package body pck is
end pck;
library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;

use work.pck.all;


entity fft is
port(
input: inout my_input_type;

O1: out my_input_type);
end fft;

architecture fft_arch of fft is
begin

process(input)
variable j,n1,temp: integer;
variable i: integer;
begin

j:= 0;
for i in 0 to 7 loop
n1 := 4;
while ( j >= n1 ) loop
j:= j - n1;
n1:= n1/2;
end loop;
j:= j + n1;

if(i < j) then
temp := input(i);
input(i) <= input(j);
input(j) <= temp;
end if;
end loop;

O1 <= input;

end process;
end fft_arch;

This is my code. I have no problems compiling it. But, wen i click run in simulate, after forcing values into port 'input', there is no output. Seems like everything's hung up.. Can anyone help me out with this..
(may be u can try copying the code into ur text editor and let me know if u r able to run in the simulate mode, without any problem)

Thank you,
Richard.

 

[TrickyDicky]

did you run the simulation for any length of time?
What kind of simulation are you you running? RTL or Post synthesis?

---------- Post added at 10:34 ---------- Previous post was at 10:33 ----------

Actually - looking at the code - what output do you get? Im guessing you got errors, because you cannot use integer as an inout port because it is not resolved.

 

[Richard Divakar Vemagiri]

Hi TrickyDicky,
I didn't get any errors. I compile the code, and it says that compilation was successful. I'm using 'ModelSim PE Student Edition 10.0' for simulating. So after compilation, i click on 'Start Simulation' and everything works well. Now wen i force values into the 'input' array and click 'run', i expect the output 'O1' array to have some values, coz that's the last line in my code saying "O1 <= input".
But, wen i click 'run', nothing happens. All the buttons like 'run','run all', etc get disabled and nothing else happens. I hope i'm making things clearer. I don't understand what's wrong. Plz let me know if u have a solution for this.
And about integer being used as an inout, u were saying that "it is not resolved". What does that mean? I'm new to VHDL and i don't know about it. Plz let me know that as well..

Thanking You,
Richard.

 

[TrickyDicky]

the simulation is probably running, and will run until you stop it, unless you run it for a specific period of time.

In VHDL, a resolution function allows a signal to be driven from two sources. The best example in VHDL is std_logic, as it is resolved. If you do this in your code:

slv <= '1';
slv <= '0';

Then in your simulation slv would be displayed as 'X' because the resolution function says that a '1' and '0' resolve to give 'X'. But most types in VHDL do not have a resolution function (std_logic is the only standard type to have a resolution function). So as integer does not have a resolution function, you'll find that modelsim wont actually let you drive an integer port declared as inout, you should get this error:

# ** Error: (vsim-3461) Cannot use 'force -drive' on unresolved signal 'sim:/play_tb/int'.

As an asside, your code makes iit look as though you dont have an understanding of Digital design. Your code looks more like a peice of software.

 

[Richard Divakar Vemagiri]

the simulation is probably running, and will run until you stop it, unless you run it for a specific period of time.

In VHDL, a resolution function allows a signal to be driven from two sources. The best example in VHDL is std_logic, as it is resolved. If you do this in your code:

slv <= '1';
slv <= '0';

Then in your simulation slv would be displayed as 'X' because the resolution function says that a '1' and '0' resolve to give 'X'. But most types in VHDL do not have a resolution function (std_logic is the only standard type to have a resolution function). So as integer does not have a resolution function, you'll find that modelsim wont actually let you drive an integer port declared as inout, you should get this error:

# ** Error: (vsim-3461) Cannot use 'force -drive' on unresolved signal 'sim:/play_tb/int'.

As an asside, your code makes iit look as though you dont have an understanding of Digital design. Your code looks more like a peice of software.

Hi TrickyDicky,
Thank you for ur reply. I am in fact, trying to write a VHDL code for an 8 point decimation in time FFT algorithm (radix-2). The code that i showed u is to bit-reverse the positions of elements in the array. Can u suggest me a way to do it? I am not able to simulate the code which i've written. Moreover, as u said.. It does look like a piece of software, coz i've never worked on VHDL b4. I'm trying to learn. plz do help me out..
Thanking You,
Richard Divakar Vemagiri.

 

[TrickyDicky]

The first step would be to forget about VHDL and learn the basics of digital electronics. When you have a better grip on this, you can use VHDL to describe a circuit.

 

[Richard Divakar Vemagiri]

In fact, this is one of my projects that i need to finish within 2-3 weeks. I don't know if i can spend time learning VHDL first, and then try implementing it!!!

 

[TrickyDicky]

Then you may be a little stuck. Because your code needs re-writing.

 

[mrflibble]

Sounds like a little real world application of the art of renegotiating deadlines might be in order.

 

[Richard Divakar Vemagiri]

Hi,
I would like to know what value 'i' takes in this code:

function CONV_INTEGER(X:std_logic_vector) return integer is
begin
for i in X'range loop
---
Consider the value passed to 'X' is of type std_logic_vector(0 to 2);

Thank you.

 

[TrickyDicky]

consider it to be

for i in 0 to 2 loop

if X was std_logic_vector 7 downto 0, the loop becomes:

for i in 7 downto 0 loop

 

[Richard Divakar Vemagiri]

Hi TrickyDicky,
Thank you for your post. But, I find X'range not working as the way you told it will be. I give 'X' a std_logic_vector(0 to 2) and say X'range for the loop variable 'i', it doesnt work. But instead if I put "for i in 0 to 2 loop", it works. Should I include any library or do anything else to make X'range work?

 

[TrickyDicky]

the 'range attribute works on any array. are you creating you own conv_integer function? this function already exists in the std_logic_unsigned/signed library.

Please post the code where you say the X'range is not working, as Im guessing you have done something wrong.