you need to declare a type. preferably within a package. eg: type my_input_type is array (natural range <>) of integer; if this is in a package, then you can include the package in every file that instantiates or defines fft.
... Sorry, but I'm new to VHDL and im' trying to learn...
the simulation is probably running, and will run until you stop it, unless you run it for a specific period of time.
In VHDL, a resolution function allows a signal to be driven from two sources. The best example in VHDL is std_logic, as it is resolved. If you do this in your code:
slv <= '1';
slv <= '0';
Then in your simulation slv would be displayed as 'X' because the resolution function says that a '1' and '0' resolve to give 'X'. But most types in VHDL do not have a resolution function (std_logic is the only standard type to have a resolution function). So as integer does not have a resolution function, you'll find that modelsim wont actually let you drive an integer port declared as inout, you should get this error:
# ** Error: (vsim-3461) Cannot use 'force -drive' on unresolved signal 'sim:/play_tb/int'.
As an asside, your code makes iit look as though you dont have an understanding of Digital design. Your code looks more like a peice of software.
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