Using only a few particular cells while synthesizing using Design compiler

[prabanjan1]

Hi all

I want to get a gate level netlist which has only 2 input type gates. I do not want gates with fan in greater than 2. How do I get this type of netlist using design compiler?.

Thanks in advance

 

[sharath666]

Include only those type of cells(2 in this case) in your target library

 

[syn_rocks]

Create a list of all the gates which you don't want to use from your db. And set a dont_touch attribute on the list. DC will not use these cells for synthesis. All tech db's, I have worked on have the number of inputs in the name as a naming convention.
So I would suggest use the cell naming convention to your advantage and filter out a list of all cells which you want to use.

set cells_needed [get_lib_cells $target_library -filter (based on naming)]
set_dont_touch [remove_from_collection [get_cells *] $cells_needed]

These commands are built into DC using the variable set_target_library_subset
Hope it helps :thumbsup:

 

[artmalik]

put don't_use on all the cells which you don't want in the netlist.