Using names to refer to bits in unsigned types - VHDL

[kureigu]

I was wondering if it was possible to set up a type in which I can address particular bits of an Unsigned signal using pre-defined names, like you might do with a type when setting up a state machine.

For example, If I had..

signal my_sig: unsigned(0 to 2)

Is it possible to set something up to enable me to do my_sig(X) <= value; to assign a value to my_sig(0)? And similarly for bit 1 and 2 using Y and Z respectively?

I was hoping doing this would just make it easier for me to keep track of signals that apply to certain buses, but I want grouped.

 

[TrickyDicky]

I dont quite understand what you mean - my_sig(0) is pretty clear. Otherwise you can just set up a constant to do it:

constant INDEX_X : integer := 0;

my_sig(INDEX_X) <= value;

or if you want to completly diversify, use an alias:

alias bit_0 : std_logic is my_sig(0);

bit_0 <= value;

Another point to note is if you're doing this, why are you using the unsigned type. Are you doing arithmatic on it later? also, unsigned types should always be decalred (N downto 0) to ensure arithmatic is done correctly.

 

[std_match]

You have at least two ways to do this:

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Code VHDL - [expand]
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constant X : integer := 0;
...
my_sig(X) <= value;

---

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Code VHDL - [expand]
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alias my_name_for_bit_0 : std_logic is my_sig(0);
...
my_name_for_bit_0 <= value;

---

 

[kureigu]

Excellent, thanks very much!

Another point to note is if you're doing this, why are you using the unsigned type. Are you doing arithmatic on it later? also, unsigned types should always be decalred (N downto 0) to ensure arithmatic is done correctly.

It was just an example, I tend to use X downto 0 for all things that require arithmetic anyway.