Using multiple MGTs in the same bank separately

[spman]

Hi,
I have a board with two SFP+ ports. These ports are connected to MGTs in the same bank of FPGA. When I use one port, everything is ok.
For utilizing two ports simultaneously, I instantiated two PCS/PMA cores in the design and pass MGTREFCLK to both of them. But I got this error:

ERROR:Place:1073 - Placer was unable to create RPM[BUFDS_RPMs] for the component
   PHY_1/ten_gig_eth_pcs_pma_block/gt_usrclk_source/grefclk_ibufds_i of type
   BUFDS for the following reason.
   The reason for this issue:
   The structured logic has to be merged with another RPM which causes a
   placement violation for component
   PHY_0/ten_gig_eth_pcs_pma_block/gt_usrclk_source/grefclk_ibufds_i. The
   following components are part of this structure:
      BUFDS   PHY_1/ten_gig_eth_pcs_pma_block/gt_usrclk_source/grefclk_ibufds_i
      IPAD   SFP_CLK_MGT_N

So I removed IBUFDS_GTE2 in both of the cores and instantiated one IBUFDS_GTE2 in the top module. But now there is another error:

ERROR:Place:1390 - Unroutable Placement! A GTXE_COMMON / GT clock component pair
   have been found that are not placed at a routable site pair. The GTXE_COMMON
   component
   <PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gthe2_common_0_i> is
   placed at site <GTHE2_COMMON_X1Y7>. The corresponding GT component
   <PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gt0_gtwizard_gth_10g
   baser_i/gthe2_i> is placed at site <GTHE2_CHANNEL_X1Y27>. The pair can use
   the fast path between them if the GTXE_COMMON and GT are both placed in the
   same clock region. You may want to analyze why this problem exists and
   correct it. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < PIN
   "PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gthe2_common_0_i.QPL
   LOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN
   "PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gt0_gtwizard_gth_10g
   baser_i/gthe2_i.QPLLCLK" CLOCK_DEDICATED_ROUTE = FALSE; >

I think the problem is because of using MGTs of same bank in different cores.
Could anyone please help me?
The FPGA is a Virtex-7

Thanks in advance.

 

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Maybe you should carefully read UG476: https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf
You're using a channel from MGT_BANK116: GTHE2_CHANNEL_X1Y27 and a common from MGT_BANK115: GTHE2_COMMON_X1Y7. They need to be in the same bank.

You should use the IP wizard to create a x2 GTH core. The wizard will correctly use a single common from the MGT_BANK_xxx and the two GTHs will reside in the same bank.

Regards

 

[spman]

Yes! There is two commons in the design. Each of the cores instantiates a GT common. But GTs are in the same quad with one common.
I don't know how to make a shared GT common. Transceiver section of the core is too complicated for me to change it.

 

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Like I said in my previous post use the wizard and generate two trsnscievers.