Using multiple memory blocks generated by coregen

[ehsan_iut]

I have written a VHDL module that uses a distributed memory core generated by coregen. In a larger design, I need to use four replicas of that module. What I did was simply instantiated that module four times. However, I need to initialize the inside memory cores with different input files. The problem is that only one xco file is generated which refers to one init file. Does anyone have any idea if I can use my module with different memory contents?

 

[ring0]

I think that you have no other choice than to generate multiple cores (or not to use cores at all).