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Using MOSFET as switch to power device

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mav1234

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Will my circuit work for the following goal?: When INPUT_N is HIGH (i.e. micro is not driving it and it is pulled up to 3.3V), VCC pin on device will have 24V. When Microcontroller drives INPUT_N to be LOW, VCC pin is at 0V (so device is off).

Should circuit below work as intended?

mosfet_switch.PNG
 

FvM

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Your circuit involves both drawing and principle design faults.

I guess, you meaned to connect the PMOS switch between 24V and VCC pin rather than make it short the power supply, distroying itself. If so, the PMOS switch has to be controlled by a 24V tolerant open drain/open collector driver, surely not an uP GPIO pin. Usually an external transistor is utilized as level converter.
 

mav1234

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Your circuit involves both drawing and principle design faults.

I guess, you meaned to connect the PMOS switch between 24V and VCC pin rather than make it short the power supply, distroying itself. If so, the PMOS switch has to be controlled by a 24V tolerant open drain/open collector driver, surely not an uP GPIO pin. Usually an external transistor is utilized as level converter.
FvM - Would this work?

http://obrazki.elektroda.pl/2845242600_1355770773.png
 

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Now you fixed the drawing error. But the pull-up has to be connected to +24V to switch the PMOS transistor off. You'll know that the µP can't drive 24V.

A possible solution is a NMOS transistor in common gate configuration. S to µP output, G to +3V3, D to PMOS gate/pull-up. Or a NPN transistor in common base with additional emitter series resistor. Or an inverting transistor level converter in common source/emitter configuration.
 

mav1234

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Thanks. Can I use the circuit here? http://www.electronics-tutorials.ws/transistor/tran_7.html

Based on the above link, can I make my circuit the following: http://postimage.org/image/4iz730wyx/

Now you fixed the drawing error. But the pull-up has to be connected to +24V to switch the PMOS transistor off. You'll know that the µP can't drive 24V.

A possible solution is a NMOS transistor in common gate configuration. S to µP output, G to +3V3, D to PMOS gate/pull-up. Or a NPN transistor in common base with additional emitter series resistor. Or an inverting transistor level converter in common source/emitter configuration.
 

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Your latest circuit idea can only work with a NMOS FET. It involves a voltage drop at the VCC series resistor and it's disspating power when switching the device off. Don't think that it's a good idea. I was under the impression to have sketched a better solution.
 

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