[SOLVED] Using `include for functions and definitions systemverilog

[BartlebyScrivener]

I have a project with multiple files. Each file uses a log2 function, and all share common parameters and typedefs. Rather than type these out repeatedly I want to have them all in one place that the files just look up.

So I created two files functions.sv and config.sv

functions.sv contains the log2 funtion, and config.sv contains parameters written as `define PARAM_NAME 5 etc.

Now, if I have `include functions.sv and `include config.sv in all my files, modelsim complains that I am trying to redifine log2, and that I am trying to define packet_t multiple times. But if I remove the include from any file, it claims it can't use log2 and that the parameters are not defined!

What is the correct way to do this please? I just want two files, one with functions, and one with paramaters, that all my files can use.

- - - Updated - - -

I managed to get it to compile for simulation by having

`include config.sv

at the top of all files, and at the top of config.sv having

`include functions.sv

So, by my reckoning, all files get those files copied into them. Which is great, except quartus doesn't like the fact that each file has a log2 function declared in it, so i have to remove

`include functions.sv

from config.sv and place it only in one file. Now quartus will synthesize it, but modelsim won't simulate it!

Is this just an awkward fact or is there a way around this?

 

[dave_59]

If you are using SystemVerilog, then you should be putting these functions and parameters in a single package, then import the package where needed.

If you must put `defines in a file, the use the standard coding convention wrapping them in an `ifdef to prevent multiple definitions

defines.svh

`ifndef DEFINES
`define DEFINES
`else

// your defines

`endif

 

[FvM]

The SystemVerilog way to provide design global functions, types and parameters would be to write and import a package.