zaidali
Newbie level 5
hi friends
i need to use a nested loop in vhdl , like this
for j in 0 to 3 loop
for i in j to 3 loop
--------
--------
end loop
end loop
but this is not acceptable in vhdl , i mean i can't use a variable in the range of a for loop , but i need to do that , so how can i solve that ?
i need to use a nested loop in vhdl , like this
for j in 0 to 3 loop
for i in j to 3 loop
--------
--------
end loop
end loop
but this is not acceptable in vhdl , i mean i can't use a variable in the range of a for loop , but i need to do that , so how can i solve that ?