In VHDL one can use different time units to schedule simulation events. For example:
Code:
x <= '0' , '1' after 2 [COLOR="#FF0000"]ns[/COLOR] , '0' after 4 [COLOR="#0000FF"]ms[/COLOR] ;
From what I know for similar purposes Verilog uses the # sign followed by the number of simulation time units.
Is there something equivalent in Verilog to my VHDL example ?
verilog has no equivalent that I know of. it gets ugly when folks try to do gate level simulations with multiple clocks/frequencies and no common multiplier can be applied.